M41T93RMY6F datasheet(32/56 Pages) STMICROELECTRONICS

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Clock operation

M41T93

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specified period, the M41T93 sets the WDF (watchdog flag) and generates a watchdog

interrupt.

The watchdog timer is reset by writing to the watchdog register. The time-out period then

starts over.

Watchdog interrupt

On the M41T93, provided that the necessary configuration bits are set, the IRQ/FT/OUT

output will be asserted when the watchdog times out (see Section 3.14 for additional

conditions which apply).

Should the watchdog time out, to de-assert the IRQ/FT/OUT output, the lower seven bits of

the watchdog register (09h) must be written. This will de-assert the output and re-initialize

the watchdog. Writing these seven bits to 0 will de-assert the output and disable the

watchdog.

A READ of the flags register will reset the watchdog flag (bit D7; register OFh) but not de-

assert the IRQ/FT/OUT output. The watchdog function is automatically disabled upon

power-up and the watchdog register is cleared.

3.8

8-bit (countdown) timer

The timer value register is an 8-bit binary countdown timer. It is enabled and disabled via the

timer control register (11h) TE bit. Other timer properties such as the source clock, or

interrupt generation are also selected in the timer control register (see Table 7). For

accurate read back of the countdown value, the serial clock (SCL) must be operating at a

frequency of at least twice the selected timer clock.

The timer control register selects one of four source clock frequencies for the timer (4096,

64, 1, or 1/60 Hz), and enables/disables the timer. The timer counts down from a software-

loaded 8-bit binary value (register 10h) and decrements to 1. On the next tick of the counter,

it reloads the timer countdown value and sets the timer flag (TF) bit. The TF bit can only be

cleared by software. When asserted, the timer flag (TF) can also be used to generate an

interrupt (IRQ/FT/OUT) on the M41T93. Writing the timer countdown value (10h) has no

effect on the TF bit or the IRQ/FT/OUT output.

3.8.1

Timer interrupt/output

On the M41T93, there are two choices for the output depending on the TI/TP configuration

bit (timer interrupt/timer pulse, bit 6, register 11h).

Normal interrupt mode

With TI/TP = 0, the output will assert like a normal interrupt, staying low until the TF bit is

cleared by software by reading the flags register (0Fh).

Free-running mode

When TI/TP is a 1, the output is a free-running waveform as depicted in Figure 16. After

being low for the specified time (as shown in Table 8), the output automatically goes high

Watchdog,

address 09h

OFIE

BMB4

BMB3

BMB2

BMB1

BMB0

RB1

RB0

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