M41T93RMY6F datasheet(30/56 Pages) STMICROELECTRONICS

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Clock operation

M41T93

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DocID12615 Rev 8

Figure 14. Crystal isolation example

Note:

The substrate pad should be tied to VSS.

3.5

Setting the alarm clock registers

Address locations 0Ah-0Eh (alarm 1) and 14h-18h (alarm 2) contain the alarm settings.

Either alarm can be configured independently to go off at a prescribed time on a specific

month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or

second. Bits RPT15–RPT11 and RPT25-RPT21 put the alarms in the repeat mode of

operation. Table 6 on page 31 shows the possible bit configurations.

Codes not listed in the table default to the once-per-second mode to quickly alert the user of

an incorrect alarm setting. When the clock information matches the alarm clock settings

based on the match criteria defined by RPT15–RPT11 and/or RPT25-RPT21, AF1 (alarm 1

flag) or AF2 (alarm 2 flag) is set. If A1IE (alarm 1 interrupt enable) is set, the alarm condition

activates the IRQ/FT/OUT output pin. To disable either of the alarms, write a '0' to the alarm

date registers and to the RPTx5–RPTx1 bits.

Note:

If the address pointer is allowed to increment to the flag register address, or the last address

written is “Alarm Seconds,” the address pointer will increment to the flag address, and an

alarm condition will not cause the interrupt/flag to occur until the address pointer is moved to

a different address.

The IRQ output is cleared by a READ of the flags register (0Fh). A subsequent READ of the

flags register is necessary to see that the value of the alarm flag has been reset to 0.

The IRQ/FT/OUT pin can also be activated in the battery backup mode. This requires the

ABE bit (alarm in backup enable) to be set (see Section 3.14.2: Backup mode for additional

conditions which apply). Once an interrupt is asserted in backup mode, it will remain true

until VCC is restored and a subsequent read of the flags register occurs.

AI11814

Crystal

XI XO

VSS

Local Grounding

Plane (Layer 2)

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