M41T93RMY6F datasheet(12/56 Pages) STMICROELECTRONICS

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Operation

M41T93

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DocID12615 Rev 8

Operation

The M41T93 clock operates as a slave device on the SPI serial bus. It is accessed by a

simple serial interface that is SPI bus-compatible. The bus signals are SCL, SDI, SDO,

and E (see Table 1 on page 7 and Figure 5 on page 10). The device is selected when the

chip enable input (E) is held low. All instructions, addresses and data are shifted serially in

and out of the chip. The most significant bit is presented first, with the data input (SDI)

sampled on the first rising edge of the clock (SCL) after the chip enable (E) goes low. The 32

bytes contained in the device can then be accessed sequentially in the following order:



1st byte: tenths/hundredths of a second register



2nd byte: seconds register



3rd byte: minutes register



4th byte: century/hours register



5th byte: day register



6th byte: date register



7th byte: month register



8th byte: year register



9th byte: digital calibration register



10th byte: watchdog register



11th - 15th bytes: alarm 1 registers



16th byte: flags register



17th byte: timer value register



18th byte: timer control register



19th byte: analog calibration register



20th byte: square wave register



21st - 25th bytes: alarm 2 registers



26th - 32nd bytes: user RAM

The M41T93 clock continually monitors VCC for an out-of tolerance condition. Should VCC

fall below VRST, the device terminates any access in progress and resets the device address

counter. Inputs to the device will not be recognized at this time to prevent erroneous data

from being written to the device from an out-of-tolerance system.

The power input will also be switched from the VCC pin to the external battery when VCC

falls below the battery back-up switchover voltage (VSO = VRST). At this time the clock

registers will be maintained by the battery supply. As system power returns and VCC rises

above VSO, the battery is disconnected, and the power supply is switched to external VCC.

The device remains write protected until tREC seconds elapse after VCC rises above

VPFD (min). For more information on battery storage life refer to application note AN1012.

2.1

SPI bus characteristics

The serial peripheral interface (SPI) bus is intended for synchronous communication

between different ICs. It consists of four signal lines: serial data input (SDI), serial data

output (SDO), serial clock (SCL) and a chip enable (E).

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