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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC560D30L3 датащи(PDF) 65 Page - STMicroelectronics |
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SPC560D30L3 датащи(HTML) 65 Page - STMicroelectronics |
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65 / 82 page  DS6494 Rev 8 65/82 SPC560D30x, SPC560D40x Electrical characteristics 77 5tA SR D Slave access time — 1/fDSPI +70 — — ns 6tDI SR D Slave SOUT disable time — 7 — — ns 7tPCSC SR D PCSx to PCSS time — 0 — — ns 8tPASC SR D PCSS to PCSx time — 0 — — ns 9tSUI SR D Data setup time for inputs Master mode 43 — — ns Slave mode 5 — — 10 tHI SR D Data hold time for inputs Master mode 0 — — ns Slave mode 2(4) —— 11 tSUO(5) CC D Data valid after SCK edge Master mode — — 32 ns Slave mode — — 52 12 tHO(5) CC D Data hold time for outputs Master mode 0 — — ns Slave mode 8 — — 1. Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad. 2. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure positive tCSCext. 3. The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive tASCext. 4. This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR. 5. SCK and SOUT configured as MEDIUM pad. Note: Operating conditions: COUT = 10 to 50 pF, SlewIN = 3.5 to 15 ns Table 44. DSPI characteristics (continued) No. Symbol C Parameter DSPI0/DSPI1 Unit Min Typ Max |
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