80

82

84

86

88

90

92

94

96

0

2

4

6

8

10

12

14

16

Output Current (A)

PowerBlock HS/LS RDS(ON) = 18mΩ/6.7mΩ

Discrete HS/LS RDS(ON) = 18mΩ/6.7mΩ

Discrete HS/LS RDS(ON) = 18mΩ/5.5mΩ

VGS = 5V

VIN = 12V

VOUT = 1.3V

LOUT = 1µH

fSW = 500kHz

TA = 25ºC

0

0.5

1

1.5

2

2.5

3

3.5

4

0

2

4

6

8

10

12

14

16

Output Current (A)

PowerBlock HS/LS RDS(ON) = 18mΩ/6.7mΩ

Discrete HS/LS RDS(ON) = 18mΩ/6.7mΩ

Discrete HS/LS RDS(ON) = 18mΩ/5.5mΩ

VGS = 5V

VIN = 12V

VOUT = 1.3V

LOUT = 1µH

fSW = 500kHz

TA = 25ºC

11

CSD87331Q3D

www.ti.com

SLPS283B – SEPTEMBER 2011 – REVISED FEBRUARY 2017

Product Folder Links: CSD87331Q3D

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Copyright © 2011–2017, Texas Instruments Incorporated

Application Information (continued)

Figure 29. Elimination of Parasitic Inductances

The combination of TI’s latest generation silicon and optimized packaging technology has created a

benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET

chipsets with lower RDS(ON). Figure 30 and Figure 31 compare the efficiency and power loss performance of the

CSD87331Q3D versus industry standard MOSFET chipsets commonly used in this type of application. This

comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The

performance of CSD87331Q3D clearly highlights the importance of considering the effective AC on-impedance

(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET

RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s power block

technology.

Figure 30. Efficiency

Figure 31. Power Loss