L99UDL01 datasheet(20/88 Pages) STMICROELECTRONICS

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Device description

L99UDL01

20/88

DS12511 Rev 5

Control loop parameters

The control loop for the current regulation is programmable. There are two parameters that

are adjustable through SPI. It should be noted that there is a default setting that will work for

the most of the lock motor applications known. These parameters are provided to aid in any

possible scenario. Typically, these parameters can be left alone:



Integral Gain, Ki, (3 bits)



Proportional Gain, Kp, (3 bits)

Integral and proportional gain settings are the standard control loop parameters for integral

gain and proportional gain. The default settings for these parameters are Ki =2-2 = 1/4, and

Kp = 26 = 64.

This register is set up for a nominal control loop. Most, if not all, applications will be stable

enough to use this default setting.

Current regulation mode can be initiated via EN_OUT rising edge or via OUT_ON bit

(register 01H) provided EN_OUT=1 and OUTx_on =0 for the timed output x. Once started, a

timed actuation can be stopped only with EN_OUT=0, fault condition, Emergency mode or

at the natural end of timers. No other time controlled output can be started when a timed

actuation is ongoing.

Current feedback

The Integrated drivers can provide a 10 bit word representing the current regulation loop

current value. This is done to provide load integrity information in addition to the CNR bit (a

current not reached, CNR, bit is set if the current in the output does not reach the regulated

current level during the entire on-time actuation).

This is a buffered value of the 10 bit up/down counter in the current regulation loop. This

information is retrieved at the falling edge of CSN when accessing the appropriate current

loop register.

The conversion of the 10 bit information found in registers 13h – 18h to a typical value of

current is a simple equation:

The current feedback can be read during the actuation phase as well as during the dynamic

braking. In the latter case, the current feedback cannot be read when the dynamic braking is

disabled for that output (DBN_x bit). The current feedback can be read for any actuated

integrated output regardless of its configuration (current mode, voltage mode and

overridden).

In indefinite braking mode, the current feedback is disabled after the first 100ms.

PWM frequency adjustment

The current regulation or PWM control PWM frequency can be adjusted to optimize the

motor current regulation. This is accomplished in 2 kHz intervals from 10 kHz to 24 kHz

using three FPWMx bits in register 00H.

Typical Current

Regx

0xA0h

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