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STA333W датащи(PDF) 31 Page - STMicroelectronics

номер детали STA333W
подробное описание детали  2 channel high-efficiency digital audio system Sound Terminal
PDF  50 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STA333W датащи(HTML) 31 Page - STMicroelectronics

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STA333W
Register description
50
LRCK double trigger protection
Actively prevents double trigger of LRCLK.
Auto EAPD on clock loss
When active will issue a power device power-down signal (EAPD) on clock loss detection.
IC power down
The PWDN register is used to put the IC in a low-power state. When PWDN is 0, the output
begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down
the power stage, then the master clock to all internal hardware except the I²C block is gated.
This puts the IC in a very low power consumption state.
External amplifier power down
The EAPD register directly disables/enables the internal power circuitry.
When EAPD = 0, the internal power section is placed in a low-power state (disabled).
Table 35. LRCK double trigger protection
Bit
R/W
RST
Name
Description
4
R/W
1
LDTE
LRCLK double trigger protection enable
Table 36. Auto EAPD on clock loss
Bit
R/W
RST
Name
Description
5
R/W
0
ECLE
Auto EAPD on clock loss
Table 37. Power down
Bit
R/W
RST
Name
Description
6R/W
1PWDN
0: power down, low-power condition
1: normal operation
Table 38. External amplifier power down
Bit
R/W
RST
Name
Description
7
R/W
1
EAPD
0: external power stage power down active
1: normal operation



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