STA333W datasheet(18/50 Pages) STMICROELECTRONICS

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I²C bus specification

STA333W

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DocID13365 Rev 3

I²C bus specification

The STA333W supports the I²C protocol via the input ports SCL and SDA. This protocol

defines any device that sends data on to the bus as a transmitter and any device that reads

the data as a receiver. The device that controls the data transfer is known as the master and

the other as the slave. The master always starts the transfer and provides the serial clock

for synchronization. The STA333W is always a slave device in all of its communications. It

supports up to 400 kb/s (fast-mode bit rate).

5.1

Communication protocol

5.1.1

Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition

while the clock is high is used to identify a START or STOP condition.

5.1.2

Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A START condition must precede any command for

data transfer.

5.1.3

Stop condition

STOP is identified by low to high transition of the data bus SDA signal while the clock signal

SCL is stable in the high state. A STOP condition terminates communication between

STA333W and the bus master.

5.1.4

Data input

During the data input the STA333W samples the SDA signal on the rising edge of clock

SCL. For correct device operation the SDA signal must be stable during the rising edge of

the clock and the data can change only when the SCL line is low.

5.2

Device addressing

To start communication between the master and the STA333W, the master must initiate a

start condition. Following this, the master sends onto the SDA line 8 bits (MSB first)

corresponding to the device-select address and read or write mode.

The 7 most significant bits are the device address identifiers, corresponding to the I²C bus

definition. In the STA333W the I²C interface has two device addresses depending on the SA

port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode and

0 for write mode. After a START condition the STA333W identifies the device address on the

SDA bus and if a match is found, acknowledges the identification during the 9th bit time.

The byte following the device identification byte is the internal space address.

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