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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STA333W датащи(PDF) 22 Page - STMicroelectronics |
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STA333W датащи(HTML) 22 Page - STMicroelectronics |
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22 / 50 page  Register description STA333W 22/50 DocID13365 Rev 3 6.1 Configuration registers (addr 0x00 to 0x05) 6.1.1 Configuration register A (addr 0x00) Master clock select The STA333W supports sample rates of 32 kHz, 44.1 kHz, 48 KHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is: 32.768 MHz for 32 kHz 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fS). The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. D7 D6 D5 D4 D3 D2 D1 D0 FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0 01 10 00 1 1 Table 9. Master clock select Bit R/W RST Name Description 0R/W 1MCS0 Master clock select: Selects the ratio between the input I²S sample frequency and the input clock. 1R/W 1MCS1 2R/W 0MCS2 Table 10. MCS bits Input sample rate fS (kHz) IR MCS[2:0] 101 100 011 010 001 000 32, 44.1, 48 00 576 * fS 128 * fS 256 * fS 384 * fS 512 * fS 768 * fS 88.2, 96 01 NA 64 * fS 128 * fS 192 * fS 256 * fS 384 * fS 176.4, 192 1X NA 32 * fS 64 * fS 96 * fS 128 * fS 192 * fS |
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