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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LM5035CMH/NOPB датащи(PDF) 4 Page - Texas Instruments |
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LM5035CMH/NOPB датащи(HTML) 4 Page - Texas Instruments |
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4 / 43 page  CS NC AGND RT COMP OVP SS HO LO PGND VCC SR1 SR2 REF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 EP RAMP CS AGND RT COMP OVP UVLO RES DLY SS HB HS HO LO PGND VCC SR2 SR1 REF VIN 1 2 3 4 5 6 7 13 14 15 16 17 18 19 8 9 10 12 11 20 EP 13 4 LM5035C SNVS631D – JANUARY 2010 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: LM5035C Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated 6 Pin Configuration and Functions PWP Package 20-Pin HTSSOP Top View NHZ Package 24-Pin WQFN Top View Pin Functions PIN I/O DESCRIPTION APPLICATION INFORMATION NAME HTSSOP WQFN RAMP 1 23 I Modulator ramp signal An external RC circuit from VIN sets the ramp slope. This pin is discharged at the conclusion of every cycle by an internal FET. Discharge is initiated by either the internal clock or the Volt • Second clamp comparator. UVLO 2 24 I Line Undervoltage Lockout An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4-V threshold the VCC and REF regulators are enabled. When UVLO reaches the 1.25-V threshold, the SS pin is released and the device enters the active mode. Hysteresis is set by an internal current sink that pulls 23 µA from the external resistor divider. OVP 3 2 I Line Overvoltage Protection An external voltage divider from the power source sets the shutdown levels. The threshold is 1.25 V. Hysteresis is set by an internal current source that sources 23 µA into the external resistor divider. COMP 4 3 I/O Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is maximum with zero input current, while 1 mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the AC voltage across the opto-coupler detector. RT 5 4 I Oscillator Frequency Control and Sync Clock Input. Normally biased at 2 V. An external resistor connected between RT and AGND sets the internal oscillator frequency. The internal oscillator can be synchronized to an external clock with a frequency higher than the free running frequency set by the RT resistor. AGND 6 5 GND Analog Ground Connect directly to Power Ground. |
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