RT =

x 6.25 x 10

9

1

FOSC

¨

©

§

- 110 ns

RFF x CFF =

TON (1 + 10%)

In 1-

2.5V

VIN

¨

©

§

-1

2.5

Ps + 0.25 Ps

In 1-

2.5V

48V

¨

©

§

-1

=

= 51.4

Ps

18

LM5035C

SNVS631D – JANUARY 2010 – REVISED OCTOBER 2016

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Copyright © 2010–2016, Texas Instruments Incorporated

Feature Description (continued)

In addition to the PWM comparator, a Volt • Second Clamp comparator also monitors the RAMP pin. If the ramp

amplitude exceeds the 2.5-V threshold of the Volt • Second Clamp comparator, the on-time is terminated. The

CFF ramp capacitor is discharged by an internal 32-Ω discharge MOSFET controlled by the V•S Clamp

comparator. If the RAMP signal does not exceed 2.5 V before the end of the clock period, then the internal clock

will enable the discharge MOSFET to reset capacitor CFF.

By proper selection of RFF and CFF values, the maximum on-time of HO and LO can be set to the desired

duration. The on-time set by the Volt • Second Clamp varies inversely to the line voltage because the RAMP

capacitor is charged by a resistor (RFF) connected to VIN while the threshold of the clamp is a fixed voltage

(2.5 V). An example will illustrate the use of the Volt • Second Clamp comparator to achieve a 50% duty cycle

limit at 200 kHz with a 48-V line input. A 50% duty cycle at a 200 kHz requires a 2.5-µs on-time. To achieve this

maximum on-time clamp level, use Equation 1.

(1)

The recommended capacitor value range for CFF is 100 pF to 1000 pF. 470 pF is a standard value that can be

paired with an 110 kΩ to approximate the desired 51.4-µs time constant. If load transient response is slowed by

the 10% margin, the RFF value can be increased. The system signal-to-noise will be slightly decreased by

increasing RFF × CFF.

8.3.10 Oscillator, Sync Capability

The LM5035C oscillator frequency is set by a single external resistor connected between the RT and AGND pins.

To set a desired oscillator frequency, the necessary RT resistor is calculated from Equation 2.

(2)

For example, if the desired oscillator frequency is 400 kHz (HO and LO each switching at 200 kHz) a 15-kΩ

resistor would be the nearest standard one percent value.

Each output (HO, LO, SR1 and SR2) switches at half the oscillator frequency. The voltage at the RT pin is

internally regulated to a nominal 2 V. The RT resistor should be located as close as possible to the IC, and

connected directly to the pins (RT and AGND). The tolerance of the external resistor, and the frequency

tolerance indicated in Electrical Characteristics, must be considered when determining the worst-case frequency

range.

The LM5035C can be synchronized to an external clock by applying a narrow pulse to the RT pin. The external

clock must be at least 10% higher than the free-running oscillator frequency set by the RT resistor. If the external

clock frequency is less than the RT resistor programmed frequency, the LM5035C will ignore the synchronizing

pulses. The synchronization pulse width at the RT pin must be a minimum of 15 ns wide. The clock signal should

be coupled into the RT pin through a 100-pF capacitor or a value small enough to ensure the pulse width at RT

is less than 60% of the clock period under all conditions. When the synchronizing pulse transitions low-to-high

(rising edge), the voltage at the RT pin must be driven to exceed 3.2 V from its nominal 2-VDC level. During the

clock signal’s low time, the voltage at the RT pin will be clamped at 2 VDC by an internal regulator. The output

impedance of the RT regulator is approximately 100 Ω. The RT resistor is always required, whether the oscillator

is free running or externally synchronized.

8.3.11 Gate Driver Outputs (HO and LO)

The LM5035C provides two alternating gate driver outputs: the floating high-side gate driver HO and the ground

referenced low-side driver LO. Each driver is capable of sourcing 1.25 A and sinking 2-A peak. The HO and LO

outputs operate in an alternating manner, at one-half the internal oscillator frequency. The LO driver is powered

directly by the VCC regulator. The HO gate driver is powered from a bootstrap capacitor connected between HB

and HS. An external diode connected between VCC (anode pin) and HB (cathode pin) provides the high-side

gate driver power by charging the bootstrap capacitor from VCC when the switch node (HS pin) is low. When the

high-side MOSFET is turned on, HB rises to a peak voltage equal to VVCC + VHS where VHS is the switch node

voltage.