GEA = AEA x

s

2SfZ1

+ 1

s

2SfZ2

+ 1

s

2SfP1

+ 1

s

2SfP2

+ 1

s

100

1k

10k

100k

1M

FREQUENCY (Hz)

-60

-44

-28

-12

4

20

100

1k

10k

100k

1M

FREQUENCY (Hz)

-150

-120

-90

-60

-30

0

VIN x RO

GPS =

VRAMP

sCORC + 1

a x s

2 + b x s + c

x

1

fESR =

2SCOESR

= 20.3 kHz

24

LM2743

SNVS276I – APRIL 2004 – REVISED FEBRUARY 2019

www.ti.com

Product Folder Links: LM2743

Submit Documentation Feedback

Copyright © 2004–2019, Texas Instruments Incorporated

Typical Applications (continued)

(32)

In the equation for fDP, the variable RL is the power stage resistance, and represents the inductor DCR plus the

on resistance of the top power MOSFET. RO is the output voltage divided by output current. The power stage

transfer function GPS is given by the following equation, and Figure 34 shows Bode plots of the phase and gain in

this example.

where

•

a = LCO(RO + RC)

•

b = L + CO(RORL + RORC + RCRL)

•

c = RO + RL

(33)

Figure 33. Gain vs Frequency

Figure 34. Power Stage Gain and Phase

The double pole at 4.5 kHz causes the phase to drop to approximately -130° at around 10 kHz. The ESR zero, at

20.3 kHz, provides a +90° boost that prevents the phase from dropping to -180º. If this loop were left

uncompensated, the bandwidth would be approximately 10 kHz and the phase margin 53°. In theory, the loop

would be stable, but would suffer from poor DC regulation (due to the low DC gain) and would be slow to

respond to load transients (due to the low bandwidth.) In practice, the loop could easily become unstable due to

tolerances in the output inductor, capacitor, or changes in output current, or input voltage. Therefore, the loop is

compensated using the error amplifier and a few passive components.

For this example, a Type III, or three-pole-two-zero approach gives optimal bandwidth and phase.

In most voltage mode compensation schemes, including Type III, a single pole is placed at the origin to boost DC

gain as high as possible. Two zeroes fZ1 and fZ2 are placed at the double pole frequency to cancel the double

pole phase lag. Then, a pole, fP1 is placed at the frequency of the ESR zero. A final pole fP2 is placed at one-half

of the switching frequency. The gain of the error amplifier transfer function is selected to give the best bandwidth

possible without violating the Nyquist stability criteria. In practice, a good crossover point is one-fifth of the

switching frequency, or 60 kHz for this example. The generic equation for the error amplifier transfer function is:

(34)