System Clock

2.6 V

2.2 V

1.8 V

Internal Reset

DOUT

Zero Data

Normal Data

Reset

VDD

Reset Removal

1024 System Clocks

4480 / fS

T0014-05

14

PCM1802

SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016

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Copyright © 2001–2016, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Hardware Control

The FMT0, FMT1, OSR, BYPASS, MD0, and MD1 pins allow the device to be controlled by tying these pins to

GPIO and GND or VDD from a host IC. These controls allow full configuration of the PCM1802.

7.3.2 Power-On Reset Sequence

The PCM1802 has an internal power-on reset circuit, and initialization (reset) is performed automatically when

the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts

after VDD > 2.2 V (typical), the PCM1802 stays in the reset state and the digital output is forced to zero. The

digital output is valid after the reset state is released and the time of 4480 / fS is passed. Figure 22 illustrates the

internal power-on reset timing and the digital output for power-on reset.

Figure 22. Internal Power-On Reset Timing

7.3.3 System Clock

The PCM1802 supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling

frequency. The system clock must be supplied on SCKI.

The PCM1802 has a system clock detection circuit which automatically senses if the system clock is operating at

256 fS, 384 fS, 512 fS, or 768 fS in slave mode. In master mode, the system clock frequency must be selected by

MODE0 and MODE1, and 768 fS is not available. For system clock inputs of 384 fS, 512 fS, and 768 fS, the

system clock is divided to 256 fS automatically, and the 256 fS clock operates the delta-sigma modulator and the

digital filter.