5

PCM1802

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SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016

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Copyright © 2001–2016, Texas Instruments Incorporated

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1)

PCM1802

UNIT

DB (SSOP)

20 PINS

RθJA

Junction-to-ambient thermal resistance

80.8

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

40

°C/W

RθJB

Junction-to-board thermal resistance

37.6

°C/W

ψJT

Junction-to-top characterization parameter

7.2

°C/W

ψJB

Junction-to-board characterization parameter

37

°C/W

(1)

Maximum system clock frequency is not applicable at 768 fS, fS = 96 kHz (see System Clock).

(2)

Applies to FSYNC, LRCK, BCK (Schmitt-trigger input in slave mode) pins.

(3)

Applies to PDWN, BYPAS, SCKI, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, 5-V tolerant) pins.

(4)

Applies to FSYNC, LRCK, BCK (Schmitt-trigger input in slave mode), SCKI (Schmitt-trigger input) pins.

(5)

Applies to PDWN, BYPAS, OSR, FMT0, FMT1, MODE0, MODE1 (Schmitt-trigger input, with 50-kΩ typical pulldown resistor) pins.

(6)

Applies to FSYNC, LRCK, BCK (in master mode), DOUT pins.

(7)

High-pass filter

6.5 Electrical Characteristics

TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

24

Bits

DATA FORMAT

Audio data interface format

Left-justified, I2S, or

right

‑justified

Audio data bit length

20 or 24

Bits

Audio data format

MSB first or 2s complement

fS

Sampling frequency

16

44.1

96

kHz

System clock frequency

256 fS

4.096

11.2896

24.576

MHz

384 fS

6.144

16.9344

36.864

512 fS

8.192

22.5792

49.152

768 fS

(1)

12.288

33.8688

INPUT LOGIC

VIH

Input logic level(2)

2

VDD

VDC

VIL

0

0.8

VIH

Input logic level(3)

2

5.5

VIL

0

0.8

IIH

Input logic current(4)

VIN = VDD

±10

µA

IIL

VIN = 0 V

±10

IIH

Input logic current(5)

VIN = VDD

65

100

IIL

VIN = 0 V

±10

OUTPUT LOGIC

VOH

Output logic level(6)

IOUT = –1 mA

2.8

VDC

VOL

IOUT = 1 mA

0.5

DC ACCURACY

Gain mismatch,

channel-to-channel

±1%

±4%

FSR

Gain error

±2%

±6%

FSR

Bipolar zero error

HPF bypassed(7)

±2%

FSR