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PCM1802

SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016

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Copyright © 2001–2016, Texas Instruments Incorporated

9 Power Supply Recommendations

The PCM1802 requires a 5-V nominal supply and a 3.3-V nominal supply. The 5-V supply is for the analog

circuitry powered by the VCC pin. The 3.3-V supply is for the digital circuitry powered by the VDD pin. The

decoupling capacitors for the power supplies must be placed close to the device pins.

10 Layout

10.1 Layout Guidelines

10.1.1 VCC and VDD Pins

The digital and analog power supply lines to the PCM1802 must be bypassed to the corresponding ground pins

with 0.1-µF ceramic and 10-µF tantalum capacitors as close to the pins as possible to maximize the dynamic

performance of the ADC.

10.1.2 AGND and DGND Pins

To maximize the dynamic performance of the PCM1802, the analog and digital grounds are not connected

internally. These grounds must have low impedance to avoid digital noise feeding back into the analog ground.

They must be connected directly to each other under the parts to reduce the potential noise problem.

10.1.3 VIN Pins

TI recommends a 1-µF capacitor for AC-coupling, which gives an 8-Hz cutoff frequency. A higher full-scale input

voltage, if required, can be accommodated by adding only one series resistor to each VIN pin.

10.1.4 VREF1 Pin

TI recommends a ceramic capacitor of 0.1 µF and an electrolytic capacitor of 10 µF between VREF1 and AGND

to ensure low source impedance for the ADC references. These capacitors must be placed as close as possible

to the VREF1 pin to reduce dynamic errors on the ADC references.

10.1.5 VREF2 Pin

The differential voltage between VREF2 and AGND sets the analog input full-scale range. TI recommends a

ceramic capacitor of 0.1 µF and an electrolytic capacitor of 10 µF between VREF2 and AGND with the insertion

of a 1-kΩ resistor between VCC and VREF2 when using a noisy analog power supply. These capacitors and

resistor are not required for a clean analog supply. These capacitors must be placed as close as possible to the

VREF2 pin to reduce dynamic errors on the ADC references. Full-scale input level is affected by this 1-kΩ

resistor, decreasing by 3%.

10.1.6 DOUT Pin

The DOUT pin has enough load drive capability, but TI recommends placing a buffer near the PCM1802 and

minimizing load capacitance if the DOUT line is long, to minimize the digital-analog crosstalk and maximize the

dynamic performance of the ADC.

10.1.7 System Clock

The quality of the system clock can influence dynamic performance, as the PCM1802 operates based on the

system clock. In slave mode, it may be necessary to consider the system-clock duty cycle, jitter, and the time

difference between the system clock transition and the BCK or LRCK transition.