BCK

FSYNC

LRCK

DOUT

t(FSSU)

t(BCKH)

t(BCKL)

t(LRHD)

t(FSHD)

t(LRCP)

t(LRSU)

t(BCKP)

t(CKDO)

t(LRDO)

1.4 V

1.4 V

1.4 V

0.5 VDD

T0017-01

18

PCM1802

SLES023D – DECEMBER 2001 – REVISED DECEMBER 2016

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Copyright © 2001–2016, Texas Instruments Incorporated

Timing measurement reference level is (VIH + VIL) / 2. Rise and fall times are measured from 10% to 90% of IN to

OUT signal swing. Load capacitance of DOUT is 20 pF.

Figure 24. Audio Data Interface Timing (Slave Mode: FSYNC, LRCK, and BCK Work as Inputs)

Table 7. Audio Data Interface Timing: Slave Mode

PARAMETER

MIN

MAX

UNIT

t(BCKP)

BCK period

150

ns

t(BCKH)

BCK pulse duration, high

60

ns

t(BCKL)

BCK pulse duration, low

60

ns

t(LRSU)

LRCK setup time to BCK rising edge

40

ns

t(LRHD)

LRCK hold time to BCK rising edge

20

ns

t(LRCP)

LRCK period

10

µs

t(FSSU)

FSYNC setup time to BCK rising edge

20

ns

t(FSHD)

FSYNC hold time to BCK rising edge

20

ns

t(CKDO)

Delay time, BCK falling edge to DOUT valid

–10

20

ns

t(LRDO)

Delay time, LRCK edge to DOUT valid

–10

20

ns

tr

Rise time of all signals

10

ns

tf

Fall time of all signals

10

ns