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CLOCK, REFERENCE, AND DATA OUTPUT MODES

INPUT CLOCK

EXTERNAL REFERENCE

VREF =1.5V+

T

V

CM

1.5V

(1)

VREF =1.5V

-

B

V

CM

1.5V

(2)

ADS5281

ADS5282

SBAS397E – DECEMBER 2006 – REVISED JANUARY 2008

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

1

X

DIFF_CLK

1

X

EN_DCC

42

1

X

EXT_REF_VCM

1

X

X

PHASE_DDR<1:0>

1

1

X

BTC_MODE

1

1

X

MSB_FIRST

46

1

1

X

EN_SDR

1

X

1

1

FALL_SDR

performance, especially at input frequencies greater than 30MHz.

In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable

an internal duty cycle correction circuit. This enabling is done by setting the EN_DCC bit to '1'.

The ADS528x can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode,

enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The

advantage of using the external reference mode is that multiple ADS528x units can be made to operate with the

same external reference, thereby improving parameters such as gain matching across devices. However, in

applications that do not have an available high drive, differential external reference, the ADS528x can still be

generated as shown in Equation 1 and Equation 2.

22

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