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DESCRIPTION OF SERIAL REGISTERS

SOFTWARE RESET

POWER-DOWN MODES

LVDS DRIVE PROGRAMMABILITY

ADS5281

ADS5282

SBAS397E – DECEMBER 2006 – REVISED JANUARY 2008

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

00

X

RST

Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears

to '0'.

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

X

X

X

X

X

X

X

X

PDN_CH<8:1>

X

PDN_PARTIAL

0F

0

X

PDN_COMPLETE

X

0

PDN_PIN_CFG

Each of the eight channels can be individually powered down. PDN_CH<N> controls the power-down mode for

the ADC channel <N>.

In addition to channel-specific power-down, the ADS528x also has two global power-down modes—partial

power-down mode and complete power-down mode. Partial power-down mode partially powers down the chip;

recovery from this mode is much quicker, provided that the clock has been running for at least 50

µs before

exiting this mode. Complete power-down mode, on the other hand, completely powers down the chip, and

involves a much longer recovery time.

In addition to programming the device for either of these two power-down modes (through either the

PDN_PARTIAL or PDN_COMPLETE bits, respectively), the PD pin itself can be configured as either a partial

power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when the

PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when the PD pin

is high, the device enters partial power-down mode.

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

X

X

X

ILVDS_LCLK<2:0>

11

X

X

X

ILVDS_FRAME<2:0>

X

X

X

ILVDS_DAT<2:0>

programmed to the same value.

18

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