ADS5281IPFPR datasheet(33/41 Pages) TI

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CLOCK INPUT

CLK

DifferentialSine-Wave,

PECL,orLVDSClockInput

0.1 F

CLK

CMOSSingle-Ended

Clock

CLK

CMOSClockInput

0.1 F

ADS5281

ADS5282

SBAS397E – DECEMBER 2006 – REVISED JANUARY 2008

The eight channels on the device operate from a

single ADCLK input. To ensure that the aperture

delay and jitter are the same for all channels, a clock

tree network is used to generate individual sampling

clocks to each channel. The clock paths for all the

channels are matched from the source point to the

sampling circuit. This architecture ensures that the

performance and timing for all channels are identical.

The use of the clock tree for matching introduces an

aperture delay that is defined as the delay between

the rising edge of ADCLK and the actual instant of

sampling. The aperture delays for all the channels

are matched to the best possible extent. A mismatch

of ±20ps (±3

σ) could exist between the aperture

instants of the eight ADCs within the same chip.

Figure 39. Internal Clock Buffer

However, the aperture delays of ADCs across two

different chips can be several hundred picoseconds

apart.

The ADS528x can be made to operate either in

CMOS

single-ended

clock

mode

(default

DIFF_CLK = 0) or differential clock mode (SINE,

LVPECL,

LVDS).

When

operating

the

single-ended clock mode, CLKN must be forced to

0VDC, and the single-ended CMOS applied on the

CLKP pin. This operation is shown in Figure 38.

Figure 40. Differential Clock Driving Circuit

(DIFF_CLK = 1)

Figure 38. Single-Ended Clock Driving Circuit

(DIFF_CLK = 0)

When configured to operate in the differential clock

Figure 41. Single-Ended Clock Driving Circuit

mode (register bit DIFF_CLK = 1) the ADS528x clock

When DIFF_CLK = 1

inputs can be driven differentially (SINE, LVPECL, or

LVDS) with little or no difference in performance

For best performance, the clock inputs must be

between them, or with a single-ended (LVCMOS).

driven

differentially,

reducing

susceptibility

The common-mode voltage of the clock inputs is set

common-mode

noise.

For

high

input

frequency

to VCM using internal 5kΩ resistors, as shown in

sampling, it is recommended to use a clock source

Figure

39.

This

method

allows

using

with very low jitter. Bandpass filtering of the clock

transformer-coupled drive circuits for a sine wave

source can help reduce the effect of jitter. If the duty

clock or ac-coupling for LVPECL and LVDS clock

cycle deviates from 50% by more than 2% or 3%, it is

sources, as shown in Figure 40. When operating in

recommended to enable the DCC through register bit

the differential clock mode, the single-ended CMOS

EN_DCC.

clock can be ac-coupled to the CLKP input, with CLKN

(pin 11) connected to ground with a 0.1

µF capacitor,

as shown in Figure 41.

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