ADS5281IPFPR datasheet(14/41 Pages) TI

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AVDD(3Vto3.6V)

LVDD(1.7Vto1.9V)

High-Level RESET

(1.4Vto3.6V)

High-Level CS

(1.4Vto3.6V)

DeviceReadyfor

SerialRegisterWrite

(2)

DeviceReadyfor

DataConversion

StartofClock

AVDD

LVDD

RESET

ADCLK

DeviceFully

PowersDown

DeviceFully

PowersUp

WAKE

1 s

ADS5281

ADS5282

SBAS397E – DECEMBER 2006 – REVISED JANUARY 2008

RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING(1)

µs < t

1 < 50ms, 10µs < t2 < 50ms, –10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns, t6 > 100ns, t7 > 10ms, and t8 > 100µs.

(1) The AVDD and LVDD power on sequence does not matter as long as –10ms < t3 < 10ms. Similar considerations apply while shutting

down the device.

(2) Write initialization registers listed in the Initialization Registers table.

POWER-DOWN TIMING

Power-up time shown is based on 1

µF bypass capacitors on the reference pins. t

WAKE is the time it takes for the device to wake up

completely from power-down mode. The ADS528x has two power-down modes: complete power-down mode and partial power-down mode.

The device can be configured in partial power-down mode through a register setting.

tWAKE < 50µs for complete power-down mode.

tWAKE < 2µs for partial power-down mode (provided the clock is not shut off during power-down).

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