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POWER-ON RESET FUNCTIONS

1024 System Clocks

Reset

Reset Removal

V

DD

Internal Reset

2.4V

2.0V

1.6V

0V

System Clock

Don’t Care

AUDIO SERIAL INTERFACE

PCM1742

SBAS176A – DECEMBER 2000 – REVISED APRIL 2005

The PCM1742 includes a power-on-reset function, as shown in Figure 20. With the system clock active and VDD

> 2 V (typical, 1.6 V to 2.4 V), the power-on-reset function is enabled. The initialization sequence requires 1024

system clocks from the time VDD > 2 V. After the initialization period, the PCM1742 is set to its reset default

state, as described in the Mode Control Registers section of this data sheet.

During the reset period (1024 system clocks), the analog outputs are forced to the bipolar zero level, or VCC/2.

After the reset period, all the mode control registers are initialized in the next 1/fS period and, if SCK, BCK, and

LRCK are provided continuously, the PCM1742 provides proper analog output with group delay corresponding to

the input data.

Figure 20. Power-On-Reset Timing

The audio serial interface for the PCM1742 comprises a 3-wire synchronous serial port. It includes LRCK (pin 3),

BCK (pin 1), and DATA (pin 2). BCK is the serial audio bit clock, which is used to clock the serial data present on

DATA into the audio interface serial shift register. Serial data is clocked into the PCM1742 on the rising edge of

BCK. LRCK is the serial audio left/right word clock used to latch serial data into the serial audio interface internal

registers.

Both LRCK and BCK must be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK

be derived from the system clock input, SCK. LRCK is operated at the sampling frequency, fS. BCK can be

operated at 32 (16-bit, right-justified only), 48, or 64 times the sampling frequency. Internal operation of the

PCM1742 is synchronized with LRCK. Accordingly, internal operation of the device is suspended when the

sampling rate clock of LRCK is changed or SCK and/or BCK is interrupted at least for three bit-clock cycles. If

SCK, BCK, and LRCK are provided continuously after this suspended state, the internal operation is

resynchronized automatically within a period of less than 3/fS. During this resynchronization period and for a 3/fS

time thereafter, the analog output is forced to the bipolar zero level, or VCC/2. External resetting is not required.

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