PCM1742ESLASH2K datasheet(31/40 Pages) TI2

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REVISION HISTORY

PCM1742

SBAS176A – DECEMBER 2000 – REVISED APRIL 2005

DATE

REV

PAGE

SECTION

DESCRIPTION

Apr 2005

–

Global

Changed to new format

Absolute Maximum Ratings

Changed values for power supply voltage, digital input voltage, lead

temperature, and package temperature. Added supply voltage

difference, VCC – VDD < 3 V.

Electrical Characteristics

Corrected maximum sampling frequency from 100 kHz to 200 kHz.

Added new values of 128 fS and 192 fS for system clock frequency.

Package/Ordering Information

Table removed from page 2, reformatted, and appended at end of

data sheet.

Recommended Operating Con-

New table added to data sheet.

ditions

Pin Assignments and Terminal

Moved from page 4

Functions

9, 10

Typical Performance Curves

In Figure 11, corrected Y-axis scale and X-axis scale.

In Figure 15, corrected frequency from 96 kHz to 192 kHz on graph

label.

System Clock Input

In Figure 19, added 1/128 fS and 1/192 fS to note for clock cycle

time.

13, 14

Audio Data Formats and Timing

In Figure 21, Audio Data Input Formats, removed 32-fS availability

from left-justified format. In Figure 22, Audio Interface Timing,

corrected specification for BCK pulse cycle time.

For Table 3, Mode Control Register Map, added note to explain the

RSV table entry.

For MUTx – Soft Mute Control, added description about in-

crementing/decrementing attenuation level by one step for every

8/fS period.

Connection Diagram

In Figure 28, corrected capacitor polarity for VDD decoupling

capacitor.

26, 27

PCB Layout Guidelines

In Figure 30 and Figure 31, deleted extraneous signal lines. In

Figure 31, changed leftmost block to Digital Logic and Audio

Processor.

Dynamic Range

Corrected parameters in test setup diagram, Figure 36.

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