www.ti.com

SYSTEM CLOCK AND RESET FUNCTIONS

SYSTEM CLOCK INPUT

t

SCKH

t

SCKL

2 V

0.8 V

System Clock

H

L

t

SCKY

PCM1742

SBAS176A – DECEMBER 2000 – REVISED APRIL 2005

The PCM1742 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma

modulators. The system clock is applied at the SCK input (pin 16). Table 1 shows examples of system clock

frequencies for common audio sampling rates.

Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important to

use a clock source with low phase jitter and noise. The PLL1700 multiclock generator from Texas Instruments is

an excellent choice for providing the PCM1742 system clock.

Table 1. System Clock Rates for Common Audio Sampling Frequencies

SAMPLING FREQUENCY

SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)

128 fS

192 fS

256 fS

384 fS

512 fS

768 fS

8 kHz

(1)

(1)

2.048

3.072

4.096

6.144

16 kHz

(1)

(1)

4.096

6.144

8.192

12.288

32 kHz

(1)

(1)

8.192

12.288

16.384

24.576

44.1 kHz

(1)

(1)

11.2896

16.9344

22.5792

33.8688

48 kHz

(1)

(1)

12.288

18.432

24.576

36.864

88.2 kHz

(1)

(1)

22.5792

33.8688

45.1584

(1)

96 kHz

(1)

(1)

24.576

36.864

49.152

(1)

192 kHz

24.576

36.864

(1)

(1)

(1)

(1)

(1)

This system clock is not supported for the given sampling frequency.

SYMBOL

DESCRIPTION

MIN

MAX

UNIT

tSCKY

System clock cycle time (1)

20

ns

tSCKH

System clock pulse duration, HIGH

7

ns

tSCKL

System clock pulse duration, LOW

7

ns

(1)

1/128 fS, 1/192 fS, 1/256 fS, 1/384 fS, 1/512 fS, or 1/768 fS

Figure 19. System Clock Input Timing

11