RG

RG

VOCM

RL

VO

RF

RF

CL

RO

EN

+

-

VI a

RM

RT

RS

RIN =

RG

1-

RF

2 * (RF + RG)

RO

SET RM = RT||RS

SET RT =

1

1

RS

-

1

RIN

¨¨

©

§

¨¨

©

§

LMP8350

www.ti.com

SNOSB80C – FEBRUARY 2011 – REVISED OCTOBER 2015

Application Information (continued)

The amplifier and ADC muist be located as close together as possible. Both devices require that the filter

components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output

traces, and the ADC is sensitive to high-frequency noise that may couple in on its input lines. Some high

performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling

process results in all input signals presented to the input stage mixing down into the Nyquist range (DC to Fs/2).

See AN-236 (SNAA079) for more details on the subsampling process and the requirements this imposes on the

filtering necessary in your system.

8.1.4 Capacitive Drive

As noted in the Driving Analog to Digital Converters section, capacitive loads should be isolated from the

amplifier output with small valued resistors. This is particularly the case when the load has a resistive component

that is 500

Ω or higher. A typical ADC has capacitive components of around 8 to 18 pF, and the resistive

component could be 1000

Ω or higher. If driving a transmission line, such as a twisted pair, using matching

resistors will be sufficient to isolate any subsequent capacitance.

8.2 Typical Application

Figure 34 shows a typical application where an LMP8350 is used to produce a differential signal from a single-

ended source.

Figure 34. Single-Ended in Differential Out

8.2.1 Design Requirements

Compared to a differential input, using a single-ended input will reduce gain by 1/2, so that the closed-loop gain

will be calculated by Equation 4:

Gain = Av = 0.5 × RF / RG

(4)

In single-ended input operation the output common-mode voltage is set by the VOCM pin. Also, In this mode the

common-mode feedback circuit must recreate the signal that is not present on the unused differential input pin.

The common-mode feedback circuit is responsible for ensuring balanced output with a single-ended input.

Balance error is defined as the amount of input signal that couples into the output common mode. It is measured

as the undesired output common-mode swing divided by the signal on the input. Balance error can be caused by

either a channel to channel gain error, or phase error. Either condition will produce a common-mode shift. The

overall bandwidth is limited due to the VOCM buffer bandwidth limitations in this configuration.

Supply and VOCM pin bypassing are also critical in this mode of operation.

8.2.2 Detailed Design Procedure

For a single-ended input differential output configuration Figure 34, component value selection is dictated by the

gain and input resistance desired. Figure 35 shows the OUT+ and OUT– relative to the single ended voltage

signal input +. Depending on the feedback resistor values, the amplitude gain of the OUT+ and OUT– will vary.

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