LMP8350

SNOSB80C – FEBRUARY 2011 – REVISED OCTOBER 2015

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7.4 Device Functional Modes

7.4.1 Enable Pin and Power Mode Selection

The LMP8350 is equipped with a four-level enable (EN) pin to select one of three power modes or shutdown.

These modes are selected by applying the appropriate voltage to the EN pin.

Each power level has a corresponding performance level. The high power mode will have the best overall BW

and distortion performance, but at the cost of higher supply current and some DC accuracy. The low power mode

has the lowest supply current, but with a noticeable loss of AC performance and output drive capabilities. The

mid-power mode provides the best balance of AC and precision DC specifications. In disable mode, the amplifier

is shutdown and the output stage goes into a high impedance state. Table 1 summarizes these performance

trade-offs.

Table 1. Performance vs. Power Mode Summary

–3dB BW

HD2

NOISE

SR

TYP VOS

MODE

VS

(MHz)

(dBc)

(nV/Hz)

(V/µS)

(mV)

10

118

–124.7

4.6

507

0.6

High

6.6

116

–124.7

4.5

488

0.3

5

114

–125.5

4.5

476

0.2

10

87

–122.8

4.8

393

0.08

Med

6.6

85

–122.8

4.8

376

0.1

5

84

–122.6

4.8

366

0.1

10

31

–117.2

8

178

0.1

Low

6.6

29

–117.2

8

166

0.1

5

28

–117

8

160

0.1

To set the mode, internally the voltage at the EN pin is compared against the total supply voltage (VS) and sets

the current consumption as shown in the table below. The EN pin voltage is referenced to the V- pin.

Table 2. Enable Pin Mode Selection

VEN

POWER

IS

VEN AT 10 V

VEN AT 6.6 V

VEN AT 5 V

(VS = V+ - V-)

MODE

mA

7/8 × VS

High

8.75

5.775

4.375

13 to 15

5/8 × VS

Med

6.25

4.125

3.125

7 to 9

3/8 × VS

Low

3.75

2.475

1.875

2 to 3

1/8 × VS

Disable

1.25

0.825

0.625

< 1

The enable pin should not be allowed to float. If the enable pin is not used it can be tied to V+ to select the high

power mode or set with two resistors.

Each power setting has a ±400-mV tolerance at each level, though TI recommends to keep the set voltage within

the center of the range as performance may vary near the transition zones.

During shutdown, both outputs are in a high impedance state, so the feedback and gain set resistors will then set

the input and output impedance of the circuit. For this reason input to output isolation will be poor in the disabled

state.

The voltage at the EN pin can be generated with a resistive voltage divider or a buffer connected to a voltage

source or a DAC. Figure 34 shows how to generate EN voltage with a resistive voltage divider.

20

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