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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LM98640CVAL датащи(PDF) 43 Page - Texas Instruments |
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LM98640CVAL датащи(HTML) 43 Page - Texas Instruments |
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43 / 55 page  43 LM98640QML-SP www.ti.com SNAS461G – MAY 2010 – REVISED NOVEMBER 2018 Product Folder Links: LM98640QML-SP Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated Table 8. Register Definitions - Timing Configuration ADDRESS (BINARY) REGISTER TITLE BASELINE (BINARY) BIT(s) DESCRIPTION 10 0000 Clamp Start 0000 1000 [7:0] Clamp Start Register. [7:6] Not Used. [5:0] CLAMP Starting Index. 0-63d position for rising edge of CLAMP signal. Valid only in CDS Mode. 10 0001 Clamp End 0001 1100 [7:0] Clamp End Register. [7:6] Not Used. [5:0] CLAMP End Index. 0-63d position for falling edge of CLAMP signal. Valid only in CDS Mode. 10 0010 Sample Start 0010 1000 [7:0] Sample Start Register. [7:6] Not Used. [5:0] SAMPLE starting Index. 0-63d position for rising edge of SAMPLE signal. 10 0011 Sample End 0011 1100 [7:0] Sample End Register. [7:6] Not Used. [5:0] SAMPLE End Index. 0-63d position for falling edge of SAMPLE signal. 10 0101 INCLK Range 0000 0010 [7:0] INCLK Range Register. [7] Not Used. [6:4] INCLK Range. 000 25 to 40 MHz Operation 001 14 to 25 MHz Operation 010 10 to 14 MHz Operation 011 7.5 to 10 MHz Operation 100 6 to 7.5 MHz Operation 101 5 to 6 MHz Operation 110 Not Used 111 Not Used [3:2] Not Used. [1:0] DLL Range 11 Reserved 10 14 to 40 MHz Operation 01 7.5 to 14 MHz Operation 00 5 to 7.5 MHz Operation 10 1000 DLL Configuration 0000 1111 [7:0] DLL Configuration Register [7:1] Reserved [0] DLL Reset. (Self Clearing) |
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