LM98640CVAL datasheet(17/55 Pages) TI2

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LM98640QML-SP

www.ti.com

SNAS461G – MAY 2010 – REVISED NOVEMBER 2018

Product Folder Links: LM98640QML-SP

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(1)

Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(2)

This parameter is ensured by design and/or characterization and is not tested.

6.7

AC Timing Specifications

The following specifications apply for VDD33 = 3.3 V, VDD18 = 1.8 V, CL = 10 pF, and fINCLK = 15 MHz unless otherwise

specified.

PARAMETER

TEST CONDITIONS

NOTES

SUB-

GROUPS

MIN

TYP(1)

MAX

UNIT

INPUT CLOCK TIMING SPECIFICATIONS

fINCLK

Input clock frequency

INCLK = ADCCLK

9, 10, 11

MHz

(ADC Rate Clock)

Tdc

Input clock duty cycle

9, 10, 11

40/60%

50/50%

60/40%

tLAT

Pipeline latency

See(2)

TADC

LVDS OUTPUT TIMING SPECIFICATIONS

tDOD

Data output delay

fINCLK = 40 MHz

INCLK = ADCCLK

(ADC Rate Clock)

LVDS Output Specifications

not tested in production.

Min/Max ensured by design,

characterization and

statistical analysis.

9, 10, 11

6.44

7.50

tDSO

Dual lane mode

9, 10, 11

0.45

0.69

Odd data setup

tDSE

Dual lane mode

9, 10, 11

0.45

0.89

Even data setup

tQSR

Quad lane mode

9, 10, 11

0.45

0.63

Data to rising clock setup

tQHF

Quad lane mode

9, 10, 11

0,45

0.53

Falling clock to data hold

SERIAL INTERFACE TIMING SPECIFICATIONS

fSCLK

Input clock frequency

fSCLK <= fINCLK

9, 10, 11

MHz

INCLK = ADCCLK

(ADC Rate Clock)

SCLK duty cycle

9, 10, 11

40/60

50/50

60/40

tIH

Input hold time

9, 10, 11

2.5

tIS

Input setup time

9, 10, 11

2.5

tSENSC

SCLK start time after SEN low

9, 10, 11

1.5

tSCSEN

SEN high after last SCLK rising

edge

9, 10, 11

2.5

tSENW

SEN pulse width

9, 10, 11

tOD

Output delay time

9, 10, 11

10.54

11.6

tHZ

Data output to high Z

9, 10, 11

1.2

1.23

TSCLK

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