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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LM98640CVAL датащи(PDF) 20 Page - Texas Instruments |
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LM98640CVAL датащи(HTML) 20 Page - Texas Instruments |
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20 / 55 page  Digital Control and Config Registers SCLK SDI SDO TXFRM- TXFRM+ TXOUT0- TXOUT0+ TXOUT1- TXOUT1+ TXOUT2- TXOUT2+ TXOUT3- TXCLK- DLL ATG 64 PGA SERIALIZER TXOUT3+ TXCLK+ PGA INTERNAL REFERENCE 14 Bit ADC 14 14 SEN OS1+ OS1- OS2+ OS2- INCLK+ INCLK- Input Bias/ Clamping PGA1[7:0] PGA2[7:0] INTERNAL REFERENCE VBG VCLP 14 Bit ADC 5 8 8 VCLP Control[4:0] VCLP Reference DAC 9 COARSE DAC FINE DAC CDAC1[8:0] FDAC1[8:0] 9 Input Bias/ Clamping CDS S/H + - CDS S/H + - 9 COARSE DAC FINE DAC CDAC2[8:0] FDAC2[8:0] 9 20 LM98640QML-SP SNAS461G – MAY 2010 – REVISED NOVEMBER 2018 www.ti.com Product Folder Links: LM98640QML-SP Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated 7 Detailed Description 7.1 Overview The LM98640QML-SP is a 14-bit, 5-MSPS to 40-MSPS, dual channel, complete Analog Front End (AFE) for digital imaging applications. The system block diagram of the LM98640QML-SP, shown in Figure 29 highlights the main features of the device. Each input has its own Input Bias and Clamping Network and Correlated Double Sample (CDS) amplifier (which can also be configure to operate in Sample/Hold Mode). Two ±8-Bit Offset DACs apply independent coarse and fine offset correction for each channel. A –3 to 18-dB Programmable Gain Amplifier (PGA) applies independent gain correction for each channel. The signals are digitized using two independent on chip high performance 14-bit, 40-MHz analog-to-digital converters. The data is finally output using a unique Serial LVDS output format that is tolerant to upsets preventing data loss. 7.2 Functional Block Diagram Figure 13. Chip Block Diagram |
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