WM8994ECSSLASHR datasheet(173/363 Pages) CIRRUS

173 / 363 page

WM8994

Rev 4.6

173

DIGITAL AUDIO INTERFACE CONTROL

This section describes the configuration of the WM8994 digital audio interface paths.

Interfaces AIF1 and AIF2 can be configured as Master or Slave, or can be tri-stated. Each input and

output signal path can be independently enabled or disabled. AIF output (digital record) and AIF input

(digital playback) paths can use a common Left/Right clock, or can use separate clocks for mixed

sample rates.

Interfaces AIF1 and AIF2 each support flexible formats, word-length, TDM configuration, channel

swapping and input path digital boost functions. 8-bit companding modes and digital loopback is also

possible.

A third interface, AIF3, is partially supported, using multiplexers to re-configure alternate connections

to AIF1 or AIF2. Note that AIF3 operates in Master mode only.

AIF1 - MASTER / SLAVE AND TRI-STATE CONTROL

The Digital Audio Interface AIF1 can operate in Master or Slave modes, selected by AIF1_MSTR. In

Master mode, the BCLK1 and LRCLK1 signals are generated by the WM8994 when one or more AIF1

channels is enabled.

When AIF1_LRCLK_FRC or AIF1_CLK_FRC is set in Master mode, then LRCLK1 and ADCLRCLK1

are output at all times, including when none of the AIF1 audio channels is enabled. Note that LRCLK1

and ADCLRCLK1 are derived from BCLK1, and either an internal or external BCLK1 signal must also

be present to generate LRCLK1 or ADCLRCLK1.

When AIF1_CLK_FRC is set in Master mode, then BCLK1 is output at all times, including when none

of the AIF1 audio channels is enabled.

The AIF1 interface can be tri-stated by setting the AIF1_TRI register. When this bit is set, then all of

the AIF1 outputs are un-driven (high-impedance). Note that the ADCLRCLK1/GPIO1 pin is a

configurable pin which may take different functions independent of AIF1. The AIF1_TRI register only

controls the ADCLRCLK1/GPIO1 pin

when its function is set to ADCLRCLK1. See “General Purpose

Input/Output

” to configure the GPIO1 pin.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R770 (0302h)

AIF1

Master/Slave

AIF1_TRI

AIF1 Audio Interface tri-state

0 = AIF1 pins operate normally

1 = Tri-state all AIF1 interface pins

Note that the GPIO1 pin is controlled by this

ADCLRCLK1.

AIF1_MSTR

AIF1 Audio Interface Master Mode Select

0 = Slave mode

1 = Master mode

AIF1_CLK_F

Forces BCLK1, LRCLK1 and ADCLRCLK1 to

be enabled when all AIF1 audio channels are

disabled.

0 = Normal

1 = BCLK1, LRCLK1 and ADCLRCLK1

always enabled in Master mode

AIF1_LRCL

K_FRC

Forces LRCLK1 and ADCLRCLK1 to be

enabled when all AIF1 audio channels are

disabled.

0 = Normal

1 = LRCLK1 and ADCLRCLK1 always

enabled in Master mode

Table 87 AIF1 Master / Slave and Tri-state Control

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