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WM8994ECS/R датащи(PDF) 169 Page - Cirrus Logic

номер детали WM8994ECS/R
подробное описание детали  Multi-channel Audio Hub CODEC for Smartphones
PDF  363 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8994ECS/R датащи(HTML) 169 Page - Cirrus Logic

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WM8994
Rev 4.6
169
n
n-1
n-2
3
2
1
n
n-1
n-2
3
2
1
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
Input Word Length (WL)
1/fs
LRCLK
BCLK
DACDAT/
ADCDAT
Figure 51 Left Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
n
n-1
n-2
3
2
1
n
n-1
n-2
3
2
1
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
Input Word Length (WL)
1/fs
LRCLK
BCLK
DACDAT/
ADCDAT
1 BCLK
1 BCLK
Figure 52 I2S Justified Audio Interface (assuming n-bit word length)
In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge
of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of LRCLK. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRCLK output will resemble the frame pulse shown in Figure 53 and
Figure 54. In device slave mode, Figure 55 and Figure 56, it is possible to use any length of frame
pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK
period before the rising edge of the next frame pulse.
n
n-1
n-2
3
2
1
n
n-1
n-2
3
2
1
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
Input Word Length (WL)
1/fs
LRCLK
BCLK
DACDAT/
ADCDAT
1 BCLK
Figure 53 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)



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