WM8994ECSSLASHR datasheet(175/363 Pages) CIRRUS

175 / 363 page

WM8994

Rev 4.6

175

When the GPIO1 pin is configured as ADCLRCLK1, then the ADCLRCLK1 frequency is controlled

relative to BCLK1 by the AIF1ADC_RATE divider. In this case, the ADCLRCLK1 is dedicated to AIF1

output, and the LRCLK1 pin is dedicated to AIF1 input, allowing different sample rates to be supported

in the two paths.

In Master mode, with GPIO1 pin configured as ADCLRCLK1, this output is enabled when any of the

AIF1 ADC channels is enabled. The ADCLRCLK1 signal can also be enabled in Slave mode, using

the AIF1ADC_LRCLK_DIR bit, allowing mixed master and slave modes.

When the GPIO1 pin is not configured as ADCLRCLK1, then the LRCLK1 signal applies to the ADC

and DAC channels, at a rate set by AIF1DAC_RATE.

See “General Purpose Input/Output” for the configuration of GPIO1. Note that, in Ultrasonic (4FS)

mode, the GPIO1 pin must be configured as ADCLRCLK1.

The BCLK1 output can be inverted using the AIF1_BCLK_INV register bit. The LRCLK1 and

ADCLRCLK1 output (when selected) can be inverted using the AIF1_LRCLK_INV register control.

Note that in Slave mode, when BCLK1 is an input, the AIF1_BCLK_INV register selects the polarity of

the received BCLK1 signal. Under default conditions, DACDAT1 input is captured on the rising edge

of BCLK1, as illustrated in Figure 5. When AIF1_BCLK_INV = 1, DACDAT1 input is captured on the

falling edge of BCLK1.

The AIF1 clock generators are controlled as illustrated in Figure 62.

AIF1 CLOCK OUTPUT CONTROL

BCLK1

enable

AIF1CLK

/AIF1_BCLK_DIV

AIF1DAC_LRCLK_DIR

BCLK1

enable

/AIF1DAC_RATE

LRCLK1

AIF1DAC1L_ENA

AIF1DAC1R_ENA

AIF1DAC2L_ENA

AIF1DAC2R_ENA

AIF1ADC1L_ENA

AIF1ADC1R_ENA

AIF1ADC2L_ENA

AIF1ADC2R_ENA

GP1_FN != 0

AIF1_CLK_FRC

AIF1ADC_LRCLK_DIR

GP1_FN != 0

AIF1_CLK_FRC

AIF1_MSTR

AIF1_LRCLK_FRC

AIF1_MSTR

AIF1ADC_LRCLK_DIR

BCLK1

enable

/AIF1ADC_RATE

ADCLRCLK1

(GPIO1)

AIF1_CLK_FRC

AIF1ADC1L_ENA

AIF1ADC1R_ENA

AIF1ADC2L_ENA

AIF1ADC2R_ENA

AIF1_LRCLK_FRC

GP1_FN = 0

Note: GPIO1 is configured as

ADCLRCLK1 when GP1_FN = 0

Note: LRCLK1 provides clocking

for the DAC and ADC channels of

AIF1 when GP1_FN != 0

Figure 62 Audio Interface 1 - BCLK and LRCLK Control

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