WM8994ECSSLASHR datasheet(174/363 Pages) CIRRUS

174 / 363 page

WM8994

174

Rev 4.6

AIF1 - SIGNAL PATH ENABLE

The AIF1 interface supports up to four input channels and up to four output channels. All enabled

channels are transmitted (on ADCDAT) or received (on DACDAT) sequentially, using time division

multiplexing (TDM).

Each of the available channels can be enabled or disabled using the register bits defined in Table 88.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (0004h)

Power

Management

(4)

AIF1ADC2L

_ENA

Enable AIF1ADC2 (Left) output path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled

AIF1ADC2R

_ENA

Enable AIF1ADC2 (Right) output path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled

AIF1ADC1L

_ENA

Enable AIF1ADC1 (Left) output path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled

AIF1ADC1R

_ENA

Enable AIF1ADC1 (Right) output path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled

R5 (0005h)

Power

Management

(5)

AIF1DAC2L

_ENA

Enable AIF1DAC2 (Left) input path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled

AIF1DAC2R

_ENA

Enable AIF1DAC2 (Right) input path (AIF1,

Timeslot 1)

0 = Disabled

1 = Enabled

AIF1DAC1L

_ENA

Enable AIF1DAC1 (Left) input path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled

AIF1DAC1R

_ENA

Enable AIF1DAC1 (Right) input path (AIF1,

Timeslot 0)

0 = Disabled

1 = Enabled

Table 88 AIF1 Signal Path Enable

AIF1 - BCLK AND LRCLK CONTROL

The BCLK1 frequency is controlled relative to AIF1CLK by the AIF1_BCLK_DIV divider.

See “Clocking

and Sample Rates

” for details of the AIF1 clock, AIF1CLK.

The LRCLK1 frequency is controlled relative to BCLK1 by the AIF1DAC_RATE divider.

In Master mode, the LRCLK1 output is generated by the WM8994 when any of the AIF1 channels is

enabled. (Note that, when GPIO1 is configured as ADCLRCLK1, then only the AIF1 DAC channels will

cause LRCLK1 to be output.)

In Slave mode, the LRCLK1 output is disabled by default to allow another digital audio interface to

drive this pin. It is also possible to force the LRCLK1 signal to be output, using the

AIF1DAC_LRCLK_DIR or AIF1ADC_LRCLK_DIR register bits, allowing mixed master and slave

modes. (Note that, when GPIO1 is configured as ADCLRCLK1, then only the AIF1DAC_LRCLK_DIR

bit will force the LRCLK1 signal.)

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