WM8994ECSSLASHR datasheet(59/363 Pages) CIRRUS

59 / 363 page

WM8994

Rev 4.6

Clocking for the Digital Microphone interface is derived from SYSCLK. The DMICCLK frequency is

configured automatically, according to the AIFn_SR, AIFnCLK_RATE and ADC_OSR128 registers.

(See “Clocking and Sample Rates” for further details of the system clocks and control registers.)

The DMICCLK is enabled whenever a digital microphone input path is enabled on the DMICDAT1 or

DMICDAT2 pin(s). Note that the SYSDSPCLK_ENA register must also be set.

When AIF1CLK is selected as the SYSCLK source (SYSCLK_SRC = 0), then the DMICCLK

frequency is controlled by the AIF1_SR and AIF1CLK_RATE registers.

When AIF2CLK is selected as the SYSCLK source (SYSCLK_SRC = 1), then the DMICCLK

frequency is controlled by the AIF2_SR and AIF2CLK_RATE registers.

The DMICCLK frequency is as described in Table 10 (for ADC_OSR128=1) and Table 11 (for

ADC_OSR128=0). The ADC_OSR128 bit is set by default, giving best audio performance. Note that

the only valid DMICCLK configurations are the ones listed in Table 10 and Table 11.

The applicable clocks (SYSCLK, and AIF1CLK or AIF2CLK) must be present and enabled when using

the digital microphone interface.

SAMPLE

RATE (kHz)

SYSCLK RATE (AIFnCLK / fs ratio)

128

192

256

384

512

768

1024

1536

2.048

11.025

2.8224

3.072

2.048

22.05

2.8224

3.072

2.048

44.1

2.8224

3.072

88.2

Note that, when ADC_OSR128=1, digital microphone operation is only supported for the above

DMICCLK configurations.

Table 10 DMICCLK Frequency (MHz) - ADC_OSR128 = 1 (Default)

SAMPLE

RATE (kHz)

SYSCLK RATE (AIFnCLK / fs ratio)

128

192

256

384

512

768

1024

1536

1.024

11.025

1.4112

1.536

1.024

22.05

1.4112

1.536

2.048

44.1

2.8224

3.072

88.2

Note that, when ADC_OSR128=0, digital microphone operation is only supported for the above

DMICCLK configurations.

Table 11 DMICCLK Frequency (MHz) - ADC_OSR128 = 0

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