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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TBD датащи(PDF) 56 Page - Freescale Semiconductor, Inc |
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TBD датащи(HTML) 56 Page - Freescale Semiconductor, Inc |
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56 / 80 page  MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 56 Figure 29 shows the RMII transmit and receive AC timing diagram. Figure 30 provides the AC test load. 2.7.10.5 SMII AC Timing Specification Figure 31 provides the AC test load. Figure 29. RMII Transmit and Receive AC Timing Figure 30. AC Test Load Table 49. SMII Mode Signal Timing Characteristics Symbol Min Max Unit ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time tSMDVKH 1.5 — ns ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time tSMDXKH 1.0 — ns ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay tSMXR 1.5 5.0 ns Notes: 1. Typical REF_CLK clock period is 8ns 2. Measured using a 5 pF load. 3. Measured using a 15 pF load 4. REF_CLK duty cycle is TBD. 5. Program GCR4 as 0x00002008 REF_CLK TXD[1–0] tRMTKHDX tRMX tRMXH tRMXR tRMXF TX_EN RXD[1–0] tRMRDXKH CRS_DV RX_ER tRMRDVKH Valid Data Output Z0 = 50 Ω VDDGE/2 RL = 50 Ω |
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