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TBD датащи(PDF) 41 Page - Freescale Semiconductor, Inc

номер детали TBD
подробное описание детали  Quad Core Digital Signal Processor
PDF  80 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

TBD датащи(HTML) 41 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
41
Figure 10 shows the DDR SDRAM output timing diagram.
Figure 11 provides the AC test load for the DDR bus.
2.7.5
Serial RapidIO Timing and SGMII Timing
2.7.5.1
AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK
Table 29 lists AC requirements.
Figure 10. DDR SDRAM Output Timing
Figure 11. DDR AC Test Load
Table 29. SDn_REF_CLK and SDn_REF_CLK AC Requirements
Parameter Description
Symbol
Min
Typical
Max
Units
Comments
REFCLK cycle time
tREF
—
10 (8, 6.4)
—
ns
8 ns applies only to serial RapidIO system
with 125-MHz reference clock. 6.4 ns
applies only to serial RapidIO systems with
a 156.25 MHz reference clock.
Note:
SGMII uses the 8 ns (125 MHz)
value only.
REFCLK cycle-to-cycle
jitter
tREFCJ
—
—
80
ps
Difference in the period of any two
adjacent REFCLK cycles
Phase jitter
tREFPJ
–40
—
40
ps
Deviation in edge location with respect to
mean edge location
ADDR/CMD
tDDKHAS, tDDKHCS
tDDKHMH
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
MCK[n]
tMCK
tDDKLDX
tDDKHDX
D1
D0
tDDKHAX ,tDDKHCX
Write A0
NOOP
tDDKHME
tDDKHMP
Output
Z0 = 50 Ω
RL = 50 Ω
VDDDDR/2



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