| поискавой системы для электроныых деталей |
|
TBD датащи(PDF) 41 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
TBD датащи(HTML) 41 Page - Freescale Semiconductor, Inc |
|
41 / 80 page ![]() Electrical Characteristics MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 41 Figure 10 shows the DDR SDRAM output timing diagram. Figure 11 provides the AC test load for the DDR bus. 2.7.5 Serial RapidIO Timing and SGMII Timing 2.7.5.1 AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK Table 29 lists AC requirements. Figure 10. DDR SDRAM Output Timing Figure 11. DDR AC Test Load Table 29. SDn_REF_CLK and SDn_REF_CLK AC Requirements Parameter Description Symbol Min Typical Max Units Comments REFCLK cycle time tREF — 10 (8, 6.4) — ns 8 ns applies only to serial RapidIO system with 125-MHz reference clock. 6.4 ns applies only to serial RapidIO systems with a 156.25 MHz reference clock. Note: SGMII uses the 8 ns (125 MHz) value only. REFCLK cycle-to-cycle jitter tREFCJ — — 80 ps Difference in the period of any two adjacent REFCLK cycles Phase jitter tREFPJ –40 — 40 ps Deviation in edge location with respect to mean edge location ADDR/CMD tDDKHAS, tDDKHCS tDDKHMH tDDKLDS tDDKHDS MDQ[x] MDQS[n] MCK[n] MCK[n] tMCK tDDKLDX tDDKHDX D1 D0 tDDKHAX ,tDDKHCX Write A0 NOOP tDDKHME tDDKHMP Output Z0 = 50 Ω RL = 50 Ω VDDDDR/2 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |