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TBD датащи(PDF) 47 Page - Freescale Semiconductor, Inc

номер детали TBD
подробное описание детали  Quad Core Digital Signal Processor
PDF  80 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

TBD датащи(HTML) 47 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
47
2.7.5.6
Receiver Eye Diagrams
For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the corresponding bit error rate
specification (Table 37, Table 38, and Table 39) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter)
falls entirely within the unshaded portion of the receiver input compliance mask shown in Figure 15 with the parameters
specified in Table 40. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the
device replaced with a 100
Ω ±5% differential resistive load.
Bit Error Rate
BER
10–12
Unit Interval
UI
320
320
ps
±100 ppm
Figure 14. Single Frequency Sinusoidal Jitter Limits
Table 39. Receiver AC Timing Specifications—3.125 GBaud (continued)
Characteristic
Symbol
Range
Unit
Notes
Min
Max
8.5 UI p-p
0.10 UI p-p
Sinusoidal
Jitter
Amplitude
22.1 kHz
1.875 MHz
20 MHz
Frequency



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