ISL70001SEH, ISL70001SRH

FN7956 Rev 3.03

Page 16 of 23

Feb 5, 2024

response, the output voltage initially deviates by an amount

shown in Equation 11.

The filter capacitors selected must have sufficiently low ESL and

ESR, such that the total output voltage deviation is less than the

maximum allowable ripple.

Most capacitor solutions rely on a mixture of high frequency

capacitors with relatively low capacitance in combination with

bulk capacitors having high capacitance but larger ESR.

Minimizing the ESL of the high-frequency capacitors allows them

to support the output voltage as the current increases.

Minimizing the ESR of the bulk capacitors allows them to supply

the increased current with less output voltage deviation.

Ceramic capacitors with X7R dielectric are recommended.

Alternately, a combination of low ESR solid tantalum capacitors

and ceramic capacitors with X7R dielectric may be used.

The ESR of the bulk capacitors is responsible for most of the

output voltage ripple. As the bulk capacitors sink and source the

inductor AC ripple current, a voltage, VP-P(MAX), develops across

the bulk capacitor according to Equation 12.

Another consideration in selecting the output capacitors is loop

stability. The total output capacitance sets the dominant pole of

the PWM. Because the ISL70001SEH, ISL70001SRH use

integrated compensation techniques, it is necessary to restrict

the output capacitance in order to optimize loop stability. The

recommended load capacitance can be estimated using

Equation 13.

Another stability requirement on the selection of the output

capacitor is that the ‘ESR zero’ (fZESR) be placed at 60kHz to

90kHz. This range is set by an internal, single compensation zero

at 8.6kHz. This ESR zero location contributes to increased phase

margin of the control loop; therefore (Equation 14):

In conclusion, the output capacitors must meet three criteria:

1. They must have sufficient bulk capacitance to sustain the

output voltage during a load transient while the output

inductor current is slewing to the value of the load transient.

2. The ESR must be sufficiently low to meet the desired output

voltage ripple due to the output inductor current.

3. The ESR zero should be placed, in a rather large range, to

provide additional phase margin.

OUTPUT INDUCTOR SELECTION

Once the output capacitors are selected, the maximum allowable

ripple voltage, VP-P(MAX), determines the lower limit on the

inductance as shown in Equation 15.

Since the output capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the transient,

the capacitor voltage becomes slightly depleted. The output

inductor must be capable of assuming the entire load current

before the output voltage decreases more than

VMAX. This

places an upper limit on inductance.

Equation 16 gives the upper limit on output inductance for the

case when the trailing edge of the current transient causes a

greater output voltage deviation than the leading edge.

Equation 17 addresses the leading edge. Normally, the trailing

edge dictates the inductance selection because duty cycles are

usually <50%. Nevertheless, both inequalities should be

evaluated, and inductance should be governed based on the

lower of the two results. In each equation, LOUT is the output

inductance, COUT is the total output capacitance, and IL(P-P) is

the peak-to-peak ripple current in the output inductor.

The other concern when selecting an output inductor is to ensure

there is adequate slope compensation when the regulator is

operated above 50% duty cycle. Since the internal slope

compensation is fixed, output inductance should satisfy

Equation 18 to ensure this requirement is met.

Input Capacitor Selection

Input capacitors are responsible for sourcing the AC component

of the input current flowing into the switching power devices.

Their RMS current capacity must be sufficient to handle the AC

component of the current drawn by the switching power devices,

which is related to duty cycle. The maximum RMS current

required by the regulator is closely approximated by Equation 19.

The important parameters to consider when selecting an input

capacitor are the voltage rating and the RMS ripple current

rating. For reliable operation, select capacitors with voltage

ratings at least 1.5x greater than the maximum input voltage.

The capacitor RMS ripple current rating should be higher than

the largest RMS ripple current required by the circuit.

Ceramic capacitors with X7R dielectric are recommended.

Alternately, a combination of low ESR solid tantalum capacitors

and ceramic capacitors with X7R dielectric may be used. The

ISL70001SEH, ISL70001SRH require a minimum effective input

capacitance of 100µF for stable operation.

V

MAX

ESL

di

dt

-----



ESR

I

STEP





+



(EQ. 11)

VP-P(MAX)

ESR

VIN VOUT

–

V

OUT

LOUT fs



VIN



-----------------------------------------------------



=

(EQ. 12)

COUT

75

F Number of LXx Pins Connected

1.8V

VOUT

----------------





=

(EQ. 13)

ESR

1

2

 f

ZESR

 C

OUT



---------------------------------------------------

=

(EQ. 14)

LOUT ESR

VIN VOUT

–

V

OUT

fs VIN



VP-P(MAX)



------------------------------------------------------





(EQ. 15)

LOUT

2COUT VOUT



I

STEP

2

--------------------------------------------

V

MAX

I

L(P-P) ESR





–



(EQ. 16)

LOUT

2COUT



I

STEP

2

-----------------------------

V

MAX

I

L(P-P) ESR





–

VIN VOUT

–







(EQ. 17)

LOUT

4.32

H

Number of LXx Pins Connected

------------------------------------------------------------------------------------------------



(EQ. 18)

IRMS MAX



VOUT

VIN

-----------------

IOUT MAX



2

1

12

------

VIN VOUT

–

LOUT fs



----------------------------------

VOUT

VIN

-----------------







 2



+









=

(EQ. 19)