ISL70001SEH, ISL70001SRH

FN7956 Rev 3.03

Page 8 of 23

Feb 5, 2024

21

FB

This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and

from FB to AGND to adjust the output voltage in accordance with Equation 2:

Where:

VOUT = Output voltage

VREF = Reference voltage (0.6V typical)

RT = Top divider resistor (Must be 1kΩ)

RB = Bottom divider resistor

The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate

SEE and to improve stability margins.

22

EN

This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and

programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a 10nF

ceramic capacitor to mitigate SEE.

23

PORSEL

This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V

supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply

voltages between 5V and 3.3V, connect this pin to DGND.

Heatsink

The heatsink is electrically isolated and should be connected to a thermal chassis of any potential which offers

optimal thermal relief.

PIN NUMBER

PIN NAME

DESCRIPTION

VOUT

VREF 1RT RB





+





=

(EQ. 2)