ISL70001SEH datasheet(13/24 Pages) RENESAS

13 / 24 page

ISL70001SEH, ISL70001SRH

FN7956 Rev 3.03

Page 13 of 23

Feb 5, 2024

clock, connect the M/S pin to DGND. In this case, the SYNC pin is

an input that accepts an external synchronizing signal. When

synchronizing multiple devices, slave regulators are synchronized

180° out-of-phase with respect to the SYNC output of a master

regulator or an external clock.

When using an ISL70001SEH in clock slave mode and applying

an external clock to SYNC (whether from a clock master

ISL70001SEH or another external clock), all the clock slaves

using the external clock signal must have their switching

disabled through their EN input before any stoppage of the clock

on the SYNC input. If the external clock signal on the SYNC pin

stops or is otherwise removed while the clock slave

ISL70001SEH is enabled, the internal lower FET turns on and

remains on as the ISL70001SEH control circuit waits for the next

rising edge of the external clock that never arrives, as shown in

Figure 8. Current from the load then recirculates through the

stuck-on lower FET. Figure 8 shows the SYNC stopping at a low

level. If the SYNC stops at a level greater than the SYNC voltage

threshold (Vth), and then decreases through the SYNC Vth, there

is a solitary LX pulse.

Operation Initialization

The ISL70001SEH, ISL70001SRH initialize based on the state of

the Power-on Reset (POR) monitor of the PVINx inputs and the

state of the EN input. Successful initialization prompts a

soft-start interval, and the regulator begins slowly ramping the

output voltage. Once the commanded output voltage is within

the proper window of operation, the power-good signal changes

state from LOW to HIGH, indicating proper regulator operation.

Power-On Reset

The POR circuitry prevents the controller from attempting to

soft-start before sufficient bias is present at the PVINx pins.

The POR threshold of the PVINx pins is controlled by the PORSEL

pin. For a nominal 5V supply voltage, PORSEL should be

connected to DVDD. For a nominal 3.3V supply voltage, PORSEL

should be connected to DGND. For nominal supply voltages

between 5V and 3.3V, PORSEL should be connected to DGND.

The POR rising and falling thresholds are shown in the “Electrical

Specifications” table on page 10.

Hysteresis between the rising and falling thresholds ensures that

small perturbations on PVINx seen during turn-on/turn-off of the

regulator do not cause inadvertent turn-off/turn-on of the

regulator. When the PVINx pins are below the POR rising

threshold, the internal synchronous power MOSFET switches are

turned off and the LXx pins are held in a high-impedance state.

Enable and Disable

After the POR input requirement is met, the ISL70001SEH,

ISL70001SRH remains in shutdown until the voltage at the

enable input rises above the enable threshold. Figure 9 shows

the enable circuit features a comparator type input. In addition to

simple logic on/off control, the enable circuit allows the level of

an external voltage to precisely gate the turn-on/turn-off of the

regulator. An internal IEN current sink with a typical value of

11µA is only active when the voltage on the EN pin is below the

enable threshold. The current sink pulls the EN pin low. As VIN2

rises, the enable level is not set exclusively by the resistor divider

from VIN2.

With the current sink active, the enable level is defined by

Equation 4. R1 is the resistor from the EN pin to VIN2 and R2 is

the resistor from the EN pin to the AGND pin.

Once the voltage at the EN pin reaches the enable threshold, the

IEN current sink turns off.

With the part enabled and the IEN current sink off, the disable

level is set by the resistor divider. The disable level is defined by

Equation 5.

The difference between the enable and disable levels provide

adjustable hysteresis so that noise on VIN2 does not interfere

with the enabling or disabling of the regulator.

To mitigate SEE, the EN pin should be bypassed to the AGND pin

with a 10nF ceramic capacitor.

FIGURE 8. SYNC LOSS SHOWING LX PULLED LOW

VOUT

SYNC

VENABLE

VR 1

-------



IEN R1



(EQ. 4)

FIGURE 9. ENABLE CIRCUIT

PVINx

VIN1

POR

LOGIC

VIN2

IEN

ENABLE

COMPARATOR

CEN

VR = 0.6V

IEN = 11µA

CEN = 10nF

VDISABLE

VR 1

-------



(EQ. 5)

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