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AX88796BLF датащи(PDF) 53 Page - ASIX Electronics Corporation |
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AX88796BLF датащи(HTML) 53 Page - ASIX Electronics Corporation |
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53 / 82 page ![]() ASIX ELECTRONICS CORPORATION 53 AX88796BLF / AX88796BLI 5.2 The Embedded PHY Registers The MII management 16-bit register set implemented is as follows. And the following sub-section will describes each field of the registers. Address Name Description Default value 0 MR0 Control 3100H 1 MR1 Status 7809H 2 MR2 PHY Identifier 1 003BH 3 MR3 PHY Identifier 2 1841H 4 MR4 Autonegotiation Advertisement 01E1H 5 MR5 Autonegotiation Link Partner Ability 0000H 6 MR6 Autonegotiation Expansion 0000H Tab - 17 The Embedded PHY Registers Key to default: Reset value 1: Bit set to logic one 0: Bit set to logic zero X: No set value Access type RO: Read only RW: Read or write Attribute SC: Self-clearing PS: Value is permanently set LL: Latch low LH: Latch high |
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