AX88796BLF datasheet(24/82 Pages) ASIX

24 / 82 page

ASIX ELECTRONICS CORPORATION

AX88796BLF / AX88796BLI

4.3 Wake-up Detection

Setting wake up Control and Status WUCS (CR page3, offset 0Ah) and D1 power saving in Power Management

data reception is disabled. And detection logic within the MAC examines receive data for three kinds of WOL

events.

Examines receive data for the pre-programmed wake-up frame patterns

Examines receive data for the Magic Packet frame patterns

Examines PHY link status change

4.3.1 Wake-up frame

AX88796B supports four programmable filters that support many different receive packet patterns. If the remote

wakeup mode is enable (in D1 sleep state). The remote wakeup function receives all frames and checks each frame

against the enabled filter and recognizes the frame as a remote wake-up frame if it passes the MAC address filtering

and CRC value match. In order to determine which bytes of the frames should be checked by the CRC-16 (x16 +x15

+x2 +1) module. AX88796B use a programmable byte mask and a programmable pattern offset for each of the four

supported filters. AX88796B also provide last byte match check and options cascade four programmable filters.

Make the four of detectors can operate simultaneously or sequentially.

The byte mask is a 32-bit field that specifies whether or not each of the 32 contiguous bytes within the frame,

beginning in the pattern offset, should be checked. If bit j in the byte mask is set, the diction logic checks byte offset

+j in the frame.

The pattern offset define on Offset 3 ~ 0 for each wake-up filter 3 ~ 0 and the real offset value equal to Offset

Last bytes 3 ~ 0 for each wake-up filter 3 ~ 0 also. The contents of Last Byte register must equal to the last of Byte

Mask bit indicates of byte value. For example, if set Byte Mask [31:0] as 00C30003h then Byte Mask [23] is the last

byte. Thus, The contents of Last byte register must equal to byte value of offset + 23.

In order to load the 32-bits of wake up control register host driver software must perform 4 writes for every 32 bit of

registers.

The first write of 8-bit is located at [31:24]. The second write will also occupy [31:24] and shift the first write of data

to [23:16]. The first write of data will be located at [7:0] after continue 4 times of write data.

8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0

Byte Mask 0

Byte Mask 1

Byte Mask 2

Byte Mask 3

Wakeup Frame 1 CRC

Wakeup Frame 0 CRC

Wakeup Frame 3 CRC

Wakeup Frame 2 CRC

Offset 3

Offset 2

Offset 1

Offset 0

Last Byte 3

Last Byte 2

Last Byte 1

Last Byte 0

Reserved

Cascade

Command

[2:0]

Command 3 Command 2 Command 1 Command 0

Wake-Up frame Byte Mask Register Structure

[31:24]

[23:16]

[15:8]

[7:0]

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