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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AX88796BLF датащи(PDF) 52 Page - ASIX Electronics Corporation |
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AX88796BLF датащи(HTML) 52 Page - ASIX Electronics Corporation |
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52 / 82 page  ASIX ELECTRONICS CORPORATION 52 AX88796BLF / AX88796BLI 5.1.73 VLAN ID 0 Register (VIDR0) Offset 1CH (Write) Field Name Description 7:0 VIDR0 VLAN ID [7:0] 5.1.74 Current TX End Page Register (CTEPR) Offset 1CH (Read) Field Name Description (Default = 00h) 7 TXCQF TX Command Queue full When set, indicate the TX Command queue was full. Host must check this status before queuing next transmit page and byte count. 6:0 CTEPR AX88796B will update CTEPR (current TX end page) After every transmitting completed without collision. It is for Host to conform how many free page can reuse for next transmitting. The value is from 40h to 7Fh. It will be 00h when reset or STP. 5.1.75 VLAN ID 1 Register (VIDR1) Offset 1DH (Write) Field Name Description 7:5 PRI Frame’s priority 4 CFI Canonical Address Frame Indicator 3:0 VIDR1 VLAN ID [11:8] 5.1.76 Big-Endian Register (BER) Offset 1EH (Write) Field Name Description (Default = 00h) 7:0 - All zero, (Default): little-endian If not all zero means set data byte order as big-endian mode. Note: This mode can be used by 32-bit big-endian mode of processors operating with an external 16-bit bus only. 5.1.77 Host Wake Up Register (HWUR) Offset 1FH (Write) Field Name Description 7:1 - Reserved 0 HWAKE (SC) Host write one to wake up AX88796B from D2 power saving. It will be auto clear when wake up. 5.1.78 Software Reset Offset 1FH (Read) Field Name Description 7:0 - Don’t care this read value. |
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