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AX88796BLF датащи(PDF) 42 Page - ASIX Electronics Corporation

номер детали AX88796BLF
подробное описание детали  Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
PDF  82 Pages
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производитель  ASIX [ASIX Electronics Corporation]
домашняя страница  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88796BLF датащи(HTML) 42 Page - ASIX Electronics Corporation

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ASIX ELECTRONICS CORPORATION
42
AX88796BLF / AX88796BLI
5.1.26 Physical Address Register 0 (PAR0)
Page1 Offset 01H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR0
Physical Address Register 0
5.1.27 Physical Address Register 1 (PAR1)
Page1 Offset 02H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR1
Physical Address Register 1
5.1.28 Physical Address Register 2 (PAR2)
Page1 Offset 03H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR2
Physical Address Register 2
5.1.29 Physical Address Register 3 (PAR3)
Page1 Offset 04H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR3
Physical Address Register 3
5.1.30 Physical Address Register 4 (PAR4)
Page1 Offset 05H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR4
Physical Address Register 4
5.1.31 Physical Address Register 5 (PAR5)
Page1 Offset 06H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
PAR5
Physical Address Register 5
The physical address registers are used to compare the destination address of incoming packets for rejecting or
accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the
sequence in PAR0 ~ PAR5 to the bit sequence of the received packet.



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