Bosch Sensortec

| BST-BMP585-DS003-02

3 | 71

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Document number: BST-BMP585-DS003-02

as well as in the event of applications for industrial property rights

4.6.4

FIFO configuration changes................................................................................................................... 25

4.7 Interrupts ............................................................................................................................................................. 25

4.7.1

Interrupt enabling ................................................................................................................................... 25

4.7.2

Interrupt sources .................................................................................................................................... 26

4.7.3

Interrupt pin ............................................................................................................................................ 27

4.8 NVM Programmability ......................................................................................................................................... 29

4.8.1

NVM User Range ................................................................................................................................... 29

5 Digital Interface........................................................................................................................................................... 30

5.1 Protocol Selection ............................................................................................................................................... 30

5.2 Interface timing.................................................................................................................................................... 30

5.2.1

Interface timing....................................................................................................................................... 31

5.2.2

I2C timing specifications......................................................................................................................... 32

5.3 Pad drive strength............................................................................................................................................... 32

5.4 Read burst address increment............................................................................................................................ 34

5.5 SPI Protocol ........................................................................................................................................................ 34

5.5.1

SPI3 Wire Mode ..................................................................................................................................... 34

5.5.2

SPI Write Operation ............................................................................................................................... 34

5.5.3

SPI read operation ................................................................................................................................. 35

5.5.4

SPI hybrid bursts.................................................................................................................................... 36

5.6 I²C protocol.......................................................................................................................................................... 37

5.6.1

I²C write operation.................................................................................................................................. 37

5.6.2

I²C read operation .................................................................................................................................. 39

5.7 I3C Protocol ........................................................................................................................................................ 41

5.7.1

I3C Identifiers ......................................................................................................................................... 41

5.7.2

I3C In-band Interrupts ............................................................................................................................ 42

5.7.3

Common Command Codes (CCC) ........................................................................................................ 42

5.7.4

I3C SDR Operations............................................................................................................................... 43

5.7.5

S0/S1 error recovery .............................................................................................................................. 44

6 Pin out and connection diagrams............................................................................................................................. 45

6.1 Pin Out ................................................................................................................................................................ 45

6.2 Connection Diagrams.......................................................................................................................................... 46

6.2.1

SPI 3-wire............................................................................................................................................... 46

6.2.2

SPI 4-wire............................................................................................................................................... 47

6.2.3

I²C........................................................................................................................................................... 47

6.2.4

I3C.......................................................................................................................................................... 48

6.2.5

SPI/I²C/I3C Configuration with VDD, VDDIO ramp-up time <10 μs....................................................... 48