ACT5101 datasheet(25/59 Pages) QORVO

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Data Sheet Rev. E, November 2019 | Subject to change without notice

25 of 59

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ACT510x

23V Buck-Boost Converter with Integrated MOSFETs

Output Voltage DVS (ACT5101 only)

The ACT5101 is ideally suited for many industry stand-

ard charging protocols such as USB PD3.0, QC2.0,

QC3.0, etc. This includes USB PD3.0 + PPD. To

achieve this compatibility, the output voltage can be dy-

namically changed. VOUT in can be dynamically

changed by writing to the VOUT[10:0] register. The

OUTPUT_SLEW[1:0] register controls the slew rate be-

tween settings when the VOUT[10:0] is changed. When

the voltage is increased, the internal ramp and regulator

can compensate and increase the voltage. However,

when the voltage is decreased, and there is no external

load on the output, the output voltage may not decrease

fast enough to the meet the requirements. To speed up

the transition time from higher to lower output voltages,

set PULLDOWN_RAMP=1. This turns on an internal

70mA load when the output voltage is stepped to a

lower voltage using the VOUT[10:0] register. The 70mA

load turns off when the voltage goes into regulation.

The ACT5101 also has a pulldown current that goes ac-

tive during any output overvoltage condition. Enable this

feature by setting the I2C bit PULLDOWN_OV = 1.

POWER ON State Machine Status

The I2C bits STATUS[2:0] in register 0x20h provide the

user with real time status of the POWER ON state ma-

chine. These bits are always 000 when the IC is not in

POWER ON mode.

Table 7: POWER ON State Machine Status

STATUS[2:0]

State Machine State

000

RST

001

010

REG

011

HICCUP

100

LL_DIS

101-111

Not Valid

Frequency

The ACT510x can operate at 125kHz, 250kHz, 500kHz,

or 1MHz. The switching frequency is set by the factory

and is not user programmable. The default frequency is

500kHz to give the best tradeoff between size and

efficiency, but can be programmed to the other options

with a custom CMI. Note that the external component

value requirements change with different switching

frequencies.

Contact

sales@active-semi.com

for

additional information about other configurations.

Input Capacitor Selection

The input is connected directly to the VIN pins. The

capacitor should be dedicated high quality, low-ESR,

ceramic capacitor that is optimally placed to minimize

the power routing. 22uF to 47uF capacitors are typically

acceptable, but the final value is application dependent.

Choose the input capacitor value to keep the input

voltage ripple less than ~50mV. The CIN input capacitor

can be increased without limit.

C 9 = I ∗

:;<=

:>? ∗@AB

:;<=

:>? C

DEF∗GHIJJKL

Where CIN is the input capacitance in uF, IOUT is the

output current in Amperes, VOUT is the output voltage in

volts, VIN is the input voltage in volts, FSW is the

switching frequency in Hz, and Vripple is the maximum

allowable input voltage ripple in volts.

If the input source is a battery, no additional capacitance

is needed. If the input source is a power supply rail,

adding an additional 100uF bulk electrolytic capacitor is

recommended.

The ceramic capacitor PCB placement is critical. Refer

to the Layout Guidelines selection and to the EVK layout

for details.

Be sure to consider the input capacitor’s DC bias effects.

A capacitor’s actual capacitance is strongly affected by

its DC bias characteristics. The input capacitor is typi-

cally an X5R, X7R, or similar dielectric. Use of Y5U, Z5U,

or similar dielectrics is not recommended. Input

capacitor placement is critical for proper operation. The

input capacitor must be placed as close to the IC as

possible. The traces from VBAT to the capacitor and

from the capacitor to PGND should as short and wide

as possible.

Output Capacitor Selection

The output capacitors are connected directly to VOUT.

The output capacitance must be a combination of

ceramic and bulk capacitance.

Table 8 gives the required capacitor values for stability.

Note that the table has two output capacitor options:

Standard Capacitance and Minimum Capacitance. The

Standard Capacitance design requires more overall

capacitance, but places no restriction on the bulk

capacitor ESR. The Minimum Capacitance design

results in an overall smaller design, but places

restrictions on the ESR. The capacitor values can be

increased without limit.

Note that the Ceramic and Bulk capacitor values are

recommended “Capacitor Values”. When choosing the

ceramic capacitors, use X5R or X7R dielectrics and be

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