TMP86CS44UG datasheet(125/172 Pages) TOSHIBA

125 / 172 page

Page 115

TMP86CS44UG

Figure 11-7 Exaple of External Clock and MSB Transmit Mode

Figure 11-8 Hold Time of the End of Transmit Mode

(4) Transmit error processing

Transmit errors occur on the following situation.

• Shift operation starts before writing next transmit data to SIOTDB in external clock opera-

tion.

If transmit errors occur during transmit operation, SIOSR<TXERR> is set to “1” immedi-

ately after starting shift operation. Synchronizing with the next serial clock falling edge,

INTSIO interrupt request is generated.

If shift operation starts before writing data to SIOTDB after SIOCR1<SIOS> is set to “1”,

SIOSR<TXERR> is set to “1” immediately after shift operation is started and then INTSIO

interrupt request is generated.

SIO pin is kept in high level when SIOSR<TXERR> is set to “1”. When transmit error

occurs, transmit operation must be forcibly stop by writing SIOCR1<SIOINH> to “1”. In

this case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are ini-

tialized.

Writing transmit

data C

Writing transmit

data B

Writing transmit

data A

A7 A6

A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0

Start shift

operation

Start shift

operation

Start shift

operation

Clearing SIOS

Writing transmit data

SIOCR1<SIOS>

SIOSR<SIOF>

SIOSR<SEF>

SCK

SO pin

SIOSR<TXF>

INTSIO

interrupt

request

SIOTDB <SIOS>

4/fc

8/fc

tSODH

SCK

SIOSR<SIOF>

SO pin

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