TMP86CS44UG datasheet(128/172 Pages) TOSHIBA

128 / 172 page

Page 118

11. Synchronous Serial Interface (SIO)

11.3 Function

TMP86CS44UG

Figure 11-11 Example of External Clock and MSB Receive Mode

(4) Receive error processing

Receive errors occur on the following situation. To protect SIORDB and the shift register contents,

the received data is ignored while the SIOSR<RXERR> is “1”.

• Shift operation is finished before reading out received data from SIORDB at SIOSR<RXF>

is “1” in an external clock operation.

If receive error occurs, set the SIOCR1<SIOS> to “0” for reading the data that received

immediately before error occurence. And read the data from SIORDB. Data in shift register

(at errors occur) can be read by reading the SIORDB again.

When SIOSR<RXERR> is cleared to “0” after reading the received data, SIOSR<RXF> is

cleared to “0”.

After clearing SIOCR1<SIOS> to “0”, when 8-bit serial clock is input to SCK pin, receive

operation is stopped. To restart the receive operation, confirm that SIOSR<SIOF> is cleared

to “0”.

If the receive error occurs, set the SIOCR1<SIOINH> to “1” for stopping the receive opera-

tion immediately. In this case, SIOCR1<SIOS>, SIOSR register, SIORDB register and

SIOTDB register are initialized.

Writing transmit

data C

Writing transmit

data B

Writing transmit

data A

A7 A6

A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0

Start shift

operation

Start shift

operation

Start shift

operation

Clearing SIOS

Reading received data

SIOCR1<SIOS>

SIOSR<SIOF>

SIOSR<SEF>

SCK

SI pin

SIOSR<RXF>

INTSIO

interrupt

request

SIORDB

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