TMP86CS44UG datasheet(17/172 Pages) TOSHIBA

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Page 7

TMP86CS44UG

2. Operational Description

2.1 CPU Core Functions

The CPU core consists of a CPU, a system clock controller, and an interrupt controller.

This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.

2.1.1 Memory Address Map

The TMP86CS44UG memory is composed MaskROM, RAM and SFR(Special function register). They are

all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86CS44UG memory address map.

Figure 2-1 Memory Address Map

2.1.2 Program Memory (MaskROM)

The TMP86CS44UG has a 61440 bytes (Address 1000H to FFFFH) of program memory (MaskROM ).

2.1.3 Data Memory (RAM)

The TMP86CS44UG has 1024bytes (Address 0040H to 043FH) of internal RAM. The first 192 bytes

(0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are

available against such an area.

The data memory contents become unstable when the power supply is turned on; therefore, the data memory

should be initialized by an initialization routine.

SFR

0000H

64 bytes

SFR:

RAM:

Special function register includes:

I/O ports

Peripheral control registers

Peripheral status registers

System control registers

Program status word

Random access memory includes:

Data memory

Stack

003FH

RAM

0040H

1024

bytes

043FH

1000H

MaskROM:

Program memory

MaskROM

61440

bytes

FFC0H

Vector table for vector call instructions

(32 bytes)

FFDFH

FFE0H

Vector table for interrupts

(32 bytes)

FFFFH

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