ADS1174IPAPR datasheet(18/35 Pages) TI

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FORMAT[2:0]

DRDY/FSYNC (SPI Format)

SERIAL INTERFACE PROTOCOLS

DRDY

SCLK

1/f

DATA

1/f

CLK

DOUT

SPI SERIAL INTERFACE

DIN

SCLK

ADS1174

ADS1178

SBAS373 – OCTOBER 2007

recommended to keep SCLK as clean as possible to

prevent glitches from accidentally shifting the data.

Data can be read from the ADS1174/78 with two

SCLK may be run as fast as the CLK frequency.

serial interface protocols (SPI or Frame-Sync) and

SCLK may be either in free-running or stop-clock

several options of data formats (TDM/Discrete and

operation

between

conversions.

For

best

Fixed/Dynamic data positions). The FORMAT[2:0]

performance, use fSCLK/fCLK ratios of 1, 1/2, 1/4, 1/8,

inputs are used to select among the options. Table 11

etc. NOTE: One CLK period is required after DRDY

lists the available options. See the DOUT Modes

falls, to start shifting data (see Timing Requirements:

section for details of the DOUT modes and data

SPI Format ).

positions.

Table 11. Data Output Format

In the SPI format, this pin functions as the DRDY

INTERFACE

DOUT

DATA

output. It goes low when data are ready for retrieval

FORMAT[2:0]

PROTOCOL

MODE

POSITION

and then returns high on the falling edge of the first

000

SPI

TDM

Dynamic

subsequent SCLK. If data are not retrieved (that is,

001

SPI

TDM

Fixed

SCLK is held low), DRDY will pulse high just before

010

SPI

Discrete

—

the next conversion data are ready, as shown in

Figure 16. The new data are loaded within one CLK

011

Frame-Sync

TDM

Dynamic

cycle before DRDY goes low. All data must be shifted

100

Frame-Sync

TDM

Fixed

out before this time to avoid being overwritten.

101

Frame-Sync

Discrete

—

Data are retrieved from the ADS1174/78 using the

serial interface. Two protocols are available: SPI and

Frame-Sync. The same pins are used for both

interfaces: SCLK,

DRDY/FSYNC,

DOUT[4:1]

(or

Figure 16. DRDY Timing with No Readback

DOUT[8:1]

for

the

ADS1178),

and

DIN.

The

FORMAT[2:0]

pins

select

the

desired

interface

protocol.

In Discrete Data Output mode, the conversion data

are output on the individual DOUT pins (DOUT1,

DOUT2, etc.), whereas in TDM mode, data are output

The SPI-compatible format is a simple read-only

only on DOUT1. The MSB data are valid on

interface. Data ready for retrieval are indicated by the

DOUT[4:1]/[8:1]

when

DRDY

goes

low.

The

falling DRDY output and are shifted out on the falling

subsequent bits are shifted out with each falling edge

edge of SCLK, MSB first. The interface can be

of SCLK. If daisy-chaining (TDM mode), the data

daisy-chained using the DIN input when using

shifted in using DIN will appear on DOUT1 after all

multiple

ADS1174/78s.

See

the

Daisy-Chaining

channel data have been shifted out.

section for more information.

This input is used when multiple ADS1174/78s are to

The serial clock (SCLK) features a Schmitt-triggered

be daisy-chained together. The DOUT1 pin of the first

input and shifts out data on DOUT on the falling

device connects to the DIN pin of the next, etc. It can

edge. It also shifts in data on the falling edge on DIN

be used with either the SPI or Frame-Sync formats.

when this pin is being used for daisy-chaining. The

Data are shifted in on the falling edge of SCLK. When

device shifts data out on the falling edge and the user

using only one ADS1174/78, tie DIN low. See the

typically shifts this data in on the rising edge. Even

Daisy-Chaining section for more information.

though

the

SCLK

input

has

hysteresis,

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