ADS1174IPAPR datasheet(12/35 Pages) TI

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PHASE RESPONSE

DATA FORMAT

SETTLING TIME

) VREF

215 * 1

* VREF

215 * 1

v −VREF

215

215 * 1

100

Conversions(1/f

DATA)

FullySettledData

at76Conversions

InitialValue

FinalValue

ADS1174

ADS1178

SBAS373 – OCTOBER 2007

The ADS1174/78 incorporates a multiple stage, linear

The ADS1174/78 outputs 16 bits of data in two’s

phase

digital

filter.

Linear

phase

filters

exhibit

complement format.

constant delay time versus input frequency (constant

A positive full-scale input produces an ideal output

group delay), which means the time delay from any

code of 7FFFh, and the negative full-scale input

instant of the input signal to the same instant of the

produces an ideal output code of 8000h. The output

output data is constant, and is independent of input

clips at these codes for signals exceeding full-scale.

signal frequency. This behavior results in essentially

Table 3 summarizes the ideal output codes for

zero phase errors when analyzing multi-tone signals.

different input signals.

Table 3. Ideal Output Code versus Input Signal

As with frequency and phase response, the digital

INPUT SIGNAL VIN

filter also determines settling time. Figure 6 shows

(AINP – AINN)

IDEAL OUTPUT CODE(1)

the output settling behavior after a step change on

≥ +VREF

7FFFh

the analog inputs normalized to conversion periods.

The X-axis is given in units of conversion. Note that

0001h

after the step change on the input occurs, the output

data changes very little prior to 30 conversion

0000h

periods. The output data is fully settled after 76

conversion periods.

FFFFh

8000h

(1) Excludes effects of noise, INL, offset, and gain errors.

Figure 6. Step Response

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